/**
  ******************************************************************************
  * @file    psram_uhs_reg.h
  * @version V1.0
  * @date    2021-07-13
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __PSRAM_UHS_REG_H__
#define __PSRAM_UHS_REG_H__

#include "bl808.h"

/* 0x0 : UHS_basic */
#define PSRAM_UHS_UHS_BASIC_OFFSET      (0x0)
#define PSRAM_UHS_REG_INIT_EN           PSRAM_UHS_REG_INIT_EN
#define PSRAM_UHS_REG_INIT_EN_POS       (0U)
#define PSRAM_UHS_REG_INIT_EN_LEN       (1U)
#define PSRAM_UHS_REG_INIT_EN_MSK       (((1U << PSRAM_UHS_REG_INIT_EN_LEN) - 1) << PSRAM_UHS_REG_INIT_EN_POS)
#define PSRAM_UHS_REG_INIT_EN_UMSK      (~(((1U << PSRAM_UHS_REG_INIT_EN_LEN) - 1) << PSRAM_UHS_REG_INIT_EN_POS))
#define PSRAM_UHS_REG_AF_EN             PSRAM_UHS_REG_AF_EN
#define PSRAM_UHS_REG_AF_EN_POS         (1U)
#define PSRAM_UHS_REG_AF_EN_LEN         (1U)
#define PSRAM_UHS_REG_AF_EN_MSK         (((1U << PSRAM_UHS_REG_AF_EN_LEN) - 1) << PSRAM_UHS_REG_AF_EN_POS)
#define PSRAM_UHS_REG_AF_EN_UMSK        (~(((1U << PSRAM_UHS_REG_AF_EN_LEN) - 1) << PSRAM_UHS_REG_AF_EN_POS))
#define PSRAM_UHS_REG_CONFIG_REQ        PSRAM_UHS_REG_CONFIG_REQ
#define PSRAM_UHS_REG_CONFIG_REQ_POS    (2U)
#define PSRAM_UHS_REG_CONFIG_REQ_LEN    (1U)
#define PSRAM_UHS_REG_CONFIG_REQ_MSK    (((1U << PSRAM_UHS_REG_CONFIG_REQ_LEN) - 1) << PSRAM_UHS_REG_CONFIG_REQ_POS)
#define PSRAM_UHS_REG_CONFIG_REQ_UMSK   (~(((1U << PSRAM_UHS_REG_CONFIG_REQ_LEN) - 1) << PSRAM_UHS_REG_CONFIG_REQ_POS))
#define PSRAM_UHS_REG_CONFIG_GNT        PSRAM_UHS_REG_CONFIG_GNT
#define PSRAM_UHS_REG_CONFIG_GNT_POS    (3U)
#define PSRAM_UHS_REG_CONFIG_GNT_LEN    (1U)
#define PSRAM_UHS_REG_CONFIG_GNT_MSK    (((1U << PSRAM_UHS_REG_CONFIG_GNT_LEN) - 1) << PSRAM_UHS_REG_CONFIG_GNT_POS)
#define PSRAM_UHS_REG_CONFIG_GNT_UMSK   (~(((1U << PSRAM_UHS_REG_CONFIG_GNT_LEN) - 1) << PSRAM_UHS_REG_CONFIG_GNT_POS))
#define PSRAM_UHS_REG_MODE_REG          PSRAM_UHS_REG_MODE_REG
#define PSRAM_UHS_REG_MODE_REG_POS      (8U)
#define PSRAM_UHS_REG_MODE_REG_LEN      (8U)
#define PSRAM_UHS_REG_MODE_REG_MSK      (((1U << PSRAM_UHS_REG_MODE_REG_LEN) - 1) << PSRAM_UHS_REG_MODE_REG_POS)
#define PSRAM_UHS_REG_MODE_REG_UMSK     (~(((1U << PSRAM_UHS_REG_MODE_REG_LEN) - 1) << PSRAM_UHS_REG_MODE_REG_POS))
#define PSRAM_UHS_REG_ADDRMB_MSK        PSRAM_UHS_REG_ADDRMB_MSK
#define PSRAM_UHS_REG_ADDRMB_MSK_POS    (16U)
#define PSRAM_UHS_REG_ADDRMB_MSK_LEN    (8U)
#define PSRAM_UHS_REG_ADDRMB_MSK_MSK    (((1U << PSRAM_UHS_REG_ADDRMB_MSK_LEN) - 1) << PSRAM_UHS_REG_ADDRMB_MSK_POS)
#define PSRAM_UHS_REG_ADDRMB_MSK_UMSK   (~(((1U << PSRAM_UHS_REG_ADDRMB_MSK_LEN) - 1) << PSRAM_UHS_REG_ADDRMB_MSK_POS))
#define PSRAM_UHS_REG_LINEAR_BND_B      PSRAM_UHS_REG_LINEAR_BND_B
#define PSRAM_UHS_REG_LINEAR_BND_B_POS  (28U)
#define PSRAM_UHS_REG_LINEAR_BND_B_LEN  (4U)
#define PSRAM_UHS_REG_LINEAR_BND_B_MSK  (((1U << PSRAM_UHS_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_UHS_REG_LINEAR_BND_B_POS)
#define PSRAM_UHS_REG_LINEAR_BND_B_UMSK (~(((1U << PSRAM_UHS_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_UHS_REG_LINEAR_BND_B_POS))

/* 0x4 : UHS_cmd */
#define PSRAM_UHS_UHS_CMD_OFFSET       (0x4)
#define PSRAM_UHS_REG_GLBR_PULSE       PSRAM_UHS_REG_GLBR_PULSE
#define PSRAM_UHS_REG_GLBR_PULSE_POS   (0U)
#define PSRAM_UHS_REG_GLBR_PULSE_LEN   (1U)
#define PSRAM_UHS_REG_GLBR_PULSE_MSK   (((1U << PSRAM_UHS_REG_GLBR_PULSE_LEN) - 1) << PSRAM_UHS_REG_GLBR_PULSE_POS)
#define PSRAM_UHS_REG_GLBR_PULSE_UMSK  (~(((1U << PSRAM_UHS_REG_GLBR_PULSE_LEN) - 1) << PSRAM_UHS_REG_GLBR_PULSE_POS))
#define PSRAM_UHS_REG_SRFI_PULSE       PSRAM_UHS_REG_SRFI_PULSE
#define PSRAM_UHS_REG_SRFI_PULSE_POS   (1U)
#define PSRAM_UHS_REG_SRFI_PULSE_LEN   (1U)
#define PSRAM_UHS_REG_SRFI_PULSE_MSK   (((1U << PSRAM_UHS_REG_SRFI_PULSE_LEN) - 1) << PSRAM_UHS_REG_SRFI_PULSE_POS)
#define PSRAM_UHS_REG_SRFI_PULSE_UMSK  (~(((1U << PSRAM_UHS_REG_SRFI_PULSE_LEN) - 1) << PSRAM_UHS_REG_SRFI_PULSE_POS))
#define PSRAM_UHS_REG_SRFO_PULSE       PSRAM_UHS_REG_SRFO_PULSE
#define PSRAM_UHS_REG_SRFO_PULSE_POS   (2U)
#define PSRAM_UHS_REG_SRFO_PULSE_LEN   (1U)
#define PSRAM_UHS_REG_SRFO_PULSE_MSK   (((1U << PSRAM_UHS_REG_SRFO_PULSE_LEN) - 1) << PSRAM_UHS_REG_SRFO_PULSE_POS)
#define PSRAM_UHS_REG_SRFO_PULSE_UMSK  (~(((1U << PSRAM_UHS_REG_SRFO_PULSE_LEN) - 1) << PSRAM_UHS_REG_SRFO_PULSE_POS))
#define PSRAM_UHS_REG_REGW_PULSE       PSRAM_UHS_REG_REGW_PULSE
#define PSRAM_UHS_REG_REGW_PULSE_POS   (3U)
#define PSRAM_UHS_REG_REGW_PULSE_LEN   (1U)
#define PSRAM_UHS_REG_REGW_PULSE_MSK   (((1U << PSRAM_UHS_REG_REGW_PULSE_LEN) - 1) << PSRAM_UHS_REG_REGW_PULSE_POS)
#define PSRAM_UHS_REG_REGW_PULSE_UMSK  (~(((1U << PSRAM_UHS_REG_REGW_PULSE_LEN) - 1) << PSRAM_UHS_REG_REGW_PULSE_POS))
#define PSRAM_UHS_REG_REGR_PULSE       PSRAM_UHS_REG_REGR_PULSE
#define PSRAM_UHS_REG_REGR_PULSE_POS   (4U)
#define PSRAM_UHS_REG_REGR_PULSE_LEN   (1U)
#define PSRAM_UHS_REG_REGR_PULSE_MSK   (((1U << PSRAM_UHS_REG_REGR_PULSE_LEN) - 1) << PSRAM_UHS_REG_REGR_PULSE_POS)
#define PSRAM_UHS_REG_REGR_PULSE_UMSK  (~(((1U << PSRAM_UHS_REG_REGR_PULSE_LEN) - 1) << PSRAM_UHS_REG_REGR_PULSE_POS))
#define PSRAM_UHS_STS_GLBR_DONE        PSRAM_UHS_STS_GLBR_DONE
#define PSRAM_UHS_STS_GLBR_DONE_POS    (8U)
#define PSRAM_UHS_STS_GLBR_DONE_LEN    (1U)
#define PSRAM_UHS_STS_GLBR_DONE_MSK    (((1U << PSRAM_UHS_STS_GLBR_DONE_LEN) - 1) << PSRAM_UHS_STS_GLBR_DONE_POS)
#define PSRAM_UHS_STS_GLBR_DONE_UMSK   (~(((1U << PSRAM_UHS_STS_GLBR_DONE_LEN) - 1) << PSRAM_UHS_STS_GLBR_DONE_POS))
#define PSRAM_UHS_STS_SRFI_DONE        PSRAM_UHS_STS_SRFI_DONE
#define PSRAM_UHS_STS_SRFI_DONE_POS    (9U)
#define PSRAM_UHS_STS_SRFI_DONE_LEN    (1U)
#define PSRAM_UHS_STS_SRFI_DONE_MSK    (((1U << PSRAM_UHS_STS_SRFI_DONE_LEN) - 1) << PSRAM_UHS_STS_SRFI_DONE_POS)
#define PSRAM_UHS_STS_SRFI_DONE_UMSK   (~(((1U << PSRAM_UHS_STS_SRFI_DONE_LEN) - 1) << PSRAM_UHS_STS_SRFI_DONE_POS))
#define PSRAM_UHS_STS_SRFO_DONE        PSRAM_UHS_STS_SRFO_DONE
#define PSRAM_UHS_STS_SRFO_DONE_POS    (10U)
#define PSRAM_UHS_STS_SRFO_DONE_LEN    (1U)
#define PSRAM_UHS_STS_SRFO_DONE_MSK    (((1U << PSRAM_UHS_STS_SRFO_DONE_LEN) - 1) << PSRAM_UHS_STS_SRFO_DONE_POS)
#define PSRAM_UHS_STS_SRFO_DONE_UMSK   (~(((1U << PSRAM_UHS_STS_SRFO_DONE_LEN) - 1) << PSRAM_UHS_STS_SRFO_DONE_POS))
#define PSRAM_UHS_STS_REGW_DONE        PSRAM_UHS_STS_REGW_DONE
#define PSRAM_UHS_STS_REGW_DONE_POS    (11U)
#define PSRAM_UHS_STS_REGW_DONE_LEN    (1U)
#define PSRAM_UHS_STS_REGW_DONE_MSK    (((1U << PSRAM_UHS_STS_REGW_DONE_LEN) - 1) << PSRAM_UHS_STS_REGW_DONE_POS)
#define PSRAM_UHS_STS_REGW_DONE_UMSK   (~(((1U << PSRAM_UHS_STS_REGW_DONE_LEN) - 1) << PSRAM_UHS_STS_REGW_DONE_POS))
#define PSRAM_UHS_STS_REGR_DONE        PSRAM_UHS_STS_REGR_DONE
#define PSRAM_UHS_STS_REGR_DONE_POS    (12U)
#define PSRAM_UHS_STS_REGR_DONE_LEN    (1U)
#define PSRAM_UHS_STS_REGR_DONE_MSK    (((1U << PSRAM_UHS_STS_REGR_DONE_LEN) - 1) << PSRAM_UHS_STS_REGR_DONE_POS)
#define PSRAM_UHS_STS_REGR_DONE_UMSK   (~(((1U << PSRAM_UHS_STS_REGR_DONE_LEN) - 1) << PSRAM_UHS_STS_REGR_DONE_POS))
#define PSRAM_UHS_STS_INIT_DONE        PSRAM_UHS_STS_INIT_DONE
#define PSRAM_UHS_STS_INIT_DONE_POS    (13U)
#define PSRAM_UHS_STS_INIT_DONE_LEN    (1U)
#define PSRAM_UHS_STS_INIT_DONE_MSK    (((1U << PSRAM_UHS_STS_INIT_DONE_LEN) - 1) << PSRAM_UHS_STS_INIT_DONE_POS)
#define PSRAM_UHS_STS_INIT_DONE_UMSK   (~(((1U << PSRAM_UHS_STS_INIT_DONE_LEN) - 1) << PSRAM_UHS_STS_INIT_DONE_POS))
#define PSRAM_UHS_STS_CONFIG_READ      PSRAM_UHS_STS_CONFIG_READ
#define PSRAM_UHS_STS_CONFIG_READ_POS  (24U)
#define PSRAM_UHS_STS_CONFIG_READ_LEN  (8U)
#define PSRAM_UHS_STS_CONFIG_READ_MSK  (((1U << PSRAM_UHS_STS_CONFIG_READ_LEN) - 1) << PSRAM_UHS_STS_CONFIG_READ_POS)
#define PSRAM_UHS_STS_CONFIG_READ_UMSK (~(((1U << PSRAM_UHS_STS_CONFIG_READ_LEN) - 1) << PSRAM_UHS_STS_CONFIG_READ_POS))

/* 0x8 : UHS_fifo_thre */
#define PSRAM_UHS_UHS_FIFO_THRE_OFFSET     (0x8)
#define PSRAM_UHS_REG_MASK_W_FIFO_CNT      PSRAM_UHS_REG_MASK_W_FIFO_CNT
#define PSRAM_UHS_REG_MASK_W_FIFO_CNT_POS  (0U)
#define PSRAM_UHS_REG_MASK_W_FIFO_CNT_LEN  (16U)
#define PSRAM_UHS_REG_MASK_W_FIFO_CNT_MSK  (((1U << PSRAM_UHS_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_UHS_REG_MASK_W_FIFO_CNT_POS)
#define PSRAM_UHS_REG_MASK_W_FIFO_CNT_UMSK (~(((1U << PSRAM_UHS_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_UHS_REG_MASK_W_FIFO_CNT_POS))
#define PSRAM_UHS_REG_MASK_R_FIFO_REM      PSRAM_UHS_REG_MASK_R_FIFO_REM
#define PSRAM_UHS_REG_MASK_R_FIFO_REM_POS  (16U)
#define PSRAM_UHS_REG_MASK_R_FIFO_REM_LEN  (16U)
#define PSRAM_UHS_REG_MASK_R_FIFO_REM_MSK  (((1U << PSRAM_UHS_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_UHS_REG_MASK_R_FIFO_REM_POS)
#define PSRAM_UHS_REG_MASK_R_FIFO_REM_UMSK (~(((1U << PSRAM_UHS_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_UHS_REG_MASK_R_FIFO_REM_POS))

/* 0xC : UHS_manual */
#define PSRAM_UHS_UHS_MANUAL_OFFSET       (0xC)
#define PSRAM_UHS_REG_FORCE_CEB_LOW       PSRAM_UHS_REG_FORCE_CEB_LOW
#define PSRAM_UHS_REG_FORCE_CEB_LOW_POS   (0U)
#define PSRAM_UHS_REG_FORCE_CEB_LOW_LEN   (1U)
#define PSRAM_UHS_REG_FORCE_CEB_LOW_MSK   (((1U << PSRAM_UHS_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_UHS_REG_FORCE_CEB_LOW_POS)
#define PSRAM_UHS_REG_FORCE_CEB_LOW_UMSK  (~(((1U << PSRAM_UHS_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_UHS_REG_FORCE_CEB_LOW_POS))
#define PSRAM_UHS_REG_FORCE_CEB_HIGH      PSRAM_UHS_REG_FORCE_CEB_HIGH
#define PSRAM_UHS_REG_FORCE_CEB_HIGH_POS  (1U)
#define PSRAM_UHS_REG_FORCE_CEB_HIGH_LEN  (1U)
#define PSRAM_UHS_REG_FORCE_CEB_HIGH_MSK  (((1U << PSRAM_UHS_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_UHS_REG_FORCE_CEB_HIGH_POS)
#define PSRAM_UHS_REG_FORCE_CEB_HIGH_UMSK (~(((1U << PSRAM_UHS_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_UHS_REG_FORCE_CEB_HIGH_POS))
#define PSRAM_UHS_REG_PSRAM_RESETB        PSRAM_UHS_REG_PSRAM_RESETB
#define PSRAM_UHS_REG_PSRAM_RESETB_POS    (2U)
#define PSRAM_UHS_REG_PSRAM_RESETB_LEN    (1U)
#define PSRAM_UHS_REG_PSRAM_RESETB_MSK    (((1U << PSRAM_UHS_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_UHS_REG_PSRAM_RESETB_POS)
#define PSRAM_UHS_REG_PSRAM_RESETB_UMSK   (~(((1U << PSRAM_UHS_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_UHS_REG_PSRAM_RESETB_POS))
#define PSRAM_UHS_REG_X16_MODE            PSRAM_UHS_REG_X16_MODE
#define PSRAM_UHS_REG_X16_MODE_POS        (3U)
#define PSRAM_UHS_REG_X16_MODE_LEN        (1U)
#define PSRAM_UHS_REG_X16_MODE_MSK        (((1U << PSRAM_UHS_REG_X16_MODE_LEN) - 1) << PSRAM_UHS_REG_X16_MODE_POS)
#define PSRAM_UHS_REG_X16_MODE_UMSK       (~(((1U << PSRAM_UHS_REG_X16_MODE_LEN) - 1) << PSRAM_UHS_REG_X16_MODE_POS))
#define PSRAM_UHS_REG_WRAP2INCR_EN        PSRAM_UHS_REG_WRAP2INCR_EN
#define PSRAM_UHS_REG_WRAP2INCR_EN_POS    (4U)
#define PSRAM_UHS_REG_WRAP2INCR_EN_LEN    (1U)
#define PSRAM_UHS_REG_WRAP2INCR_EN_MSK    (((1U << PSRAM_UHS_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_UHS_REG_WRAP2INCR_EN_POS)
#define PSRAM_UHS_REG_WRAP2INCR_EN_UMSK   (~(((1U << PSRAM_UHS_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_UHS_REG_WRAP2INCR_EN_POS))
#define PSRAM_UHS_REG_PCK_S_DIV           PSRAM_UHS_REG_PCK_S_DIV
#define PSRAM_UHS_REG_PCK_S_DIV_POS       (16U)
#define PSRAM_UHS_REG_PCK_S_DIV_LEN       (3U)
#define PSRAM_UHS_REG_PCK_S_DIV_MSK       (((1U << PSRAM_UHS_REG_PCK_S_DIV_LEN) - 1) << PSRAM_UHS_REG_PCK_S_DIV_POS)
#define PSRAM_UHS_REG_PCK_S_DIV_UMSK      (~(((1U << PSRAM_UHS_REG_PCK_S_DIV_LEN) - 1) << PSRAM_UHS_REG_PCK_S_DIV_POS))
#define PSRAM_UHS_REG_PCK_T_DIV           PSRAM_UHS_REG_PCK_T_DIV
#define PSRAM_UHS_REG_PCK_T_DIV_POS       (24U)
#define PSRAM_UHS_REG_PCK_T_DIV_LEN       (8U)
#define PSRAM_UHS_REG_PCK_T_DIV_MSK       (((1U << PSRAM_UHS_REG_PCK_T_DIV_LEN) - 1) << PSRAM_UHS_REG_PCK_T_DIV_POS)
#define PSRAM_UHS_REG_PCK_T_DIV_UMSK      (~(((1U << PSRAM_UHS_REG_PCK_T_DIV_LEN) - 1) << PSRAM_UHS_REG_PCK_T_DIV_POS))

/* 0x10 : UHS_auto_fresh_1 */
#define PSRAM_UHS_UHS_AUTO_FRESH_1_OFFSET (0x10)
#define PSRAM_UHS_REG_WIN_CYCLE           PSRAM_UHS_REG_WIN_CYCLE
#define PSRAM_UHS_REG_WIN_CYCLE_POS       (0U)
#define PSRAM_UHS_REG_WIN_CYCLE_LEN       (28U)
#define PSRAM_UHS_REG_WIN_CYCLE_MSK       (((1U << PSRAM_UHS_REG_WIN_CYCLE_LEN) - 1) << PSRAM_UHS_REG_WIN_CYCLE_POS)
#define PSRAM_UHS_REG_WIN_CYCLE_UMSK      (~(((1U << PSRAM_UHS_REG_WIN_CYCLE_LEN) - 1) << PSRAM_UHS_REG_WIN_CYCLE_POS))

/* 0x14 : UHS_auto_fresh_2 */
#define PSRAM_UHS_UHS_AUTO_FRESH_2_OFFSET (0x14)
#define PSRAM_UHS_REG_REFI_CYCLE          PSRAM_UHS_REG_REFI_CYCLE
#define PSRAM_UHS_REG_REFI_CYCLE_POS      (0U)
#define PSRAM_UHS_REG_REFI_CYCLE_LEN      (16U)
#define PSRAM_UHS_REG_REFI_CYCLE_MSK      (((1U << PSRAM_UHS_REG_REFI_CYCLE_LEN) - 1) << PSRAM_UHS_REG_REFI_CYCLE_POS)
#define PSRAM_UHS_REG_REFI_CYCLE_UMSK     (~(((1U << PSRAM_UHS_REG_REFI_CYCLE_LEN) - 1) << PSRAM_UHS_REG_REFI_CYCLE_POS))
#define PSRAM_UHS_REG_WIN_REF_CNT         PSRAM_UHS_REG_WIN_REF_CNT
#define PSRAM_UHS_REG_WIN_REF_CNT_POS     (16U)
#define PSRAM_UHS_REG_WIN_REF_CNT_LEN     (13U)
#define PSRAM_UHS_REG_WIN_REF_CNT_MSK     (((1U << PSRAM_UHS_REG_WIN_REF_CNT_LEN) - 1) << PSRAM_UHS_REG_WIN_REF_CNT_POS)
#define PSRAM_UHS_REG_WIN_REF_CNT_UMSK    (~(((1U << PSRAM_UHS_REG_WIN_REF_CNT_LEN) - 1) << PSRAM_UHS_REG_WIN_REF_CNT_POS))

/* 0x18 : UHS_auto_fresh_3 */
#define PSRAM_UHS_UHS_AUTO_FRESH_3_OFFSET (0x18)
#define PSRAM_UHS_REG_AUTO_REF_THRE       PSRAM_UHS_REG_AUTO_REF_THRE
#define PSRAM_UHS_REG_AUTO_REF_THRE_POS   (0U)
#define PSRAM_UHS_REG_AUTO_REF_THRE_LEN   (12U)
#define PSRAM_UHS_REG_AUTO_REF_THRE_MSK   (((1U << PSRAM_UHS_REG_AUTO_REF_THRE_LEN) - 1) << PSRAM_UHS_REG_AUTO_REF_THRE_POS)
#define PSRAM_UHS_REG_AUTO_REF_THRE_UMSK  (~(((1U << PSRAM_UHS_REG_AUTO_REF_THRE_LEN) - 1) << PSRAM_UHS_REG_AUTO_REF_THRE_POS))
#define PSRAM_UHS_AUTO_REFRESH_LEVEL      PSRAM_UHS_AUTO_REFRESH_LEVEL
#define PSRAM_UHS_AUTO_REFRESH_LEVEL_POS  (16U)
#define PSRAM_UHS_AUTO_REFRESH_LEVEL_LEN  (12U)
#define PSRAM_UHS_AUTO_REFRESH_LEVEL_MSK  (((1U << PSRAM_UHS_AUTO_REFRESH_LEVEL_LEN) - 1) << PSRAM_UHS_AUTO_REFRESH_LEVEL_POS)
#define PSRAM_UHS_AUTO_REFRESH_LEVEL_UMSK (~(((1U << PSRAM_UHS_AUTO_REFRESH_LEVEL_LEN) - 1) << PSRAM_UHS_AUTO_REFRESH_LEVEL_POS))

/* 0x1C : UHS_auto_fresh_4 */
#define PSRAM_UHS_UHS_AUTO_FRESH_4_OFFSET (0x1C)
#define PSRAM_UHS_REG_BUST_CYCLE          PSRAM_UHS_REG_BUST_CYCLE
#define PSRAM_UHS_REG_BUST_CYCLE_POS      (0U)
#define PSRAM_UHS_REG_BUST_CYCLE_LEN      (7U)
#define PSRAM_UHS_REG_BUST_CYCLE_MSK      (((1U << PSRAM_UHS_REG_BUST_CYCLE_LEN) - 1) << PSRAM_UHS_REG_BUST_CYCLE_POS)
#define PSRAM_UHS_REG_BUST_CYCLE_UMSK     (~(((1U << PSRAM_UHS_REG_BUST_CYCLE_LEN) - 1) << PSRAM_UHS_REG_BUST_CYCLE_POS))

/* 0x20 : UHS_psram_configure */
#define PSRAM_UHS_UHS_PSRAM_CONFIGURE_OFFSET (0x20)
#define PSRAM_UHS_REG_UHS_LATENCY            PSRAM_UHS_REG_UHS_LATENCY
#define PSRAM_UHS_REG_UHS_LATENCY_POS        (0U)
#define PSRAM_UHS_REG_UHS_LATENCY_LEN        (3U)
#define PSRAM_UHS_REG_UHS_LATENCY_MSK        (((1U << PSRAM_UHS_REG_UHS_LATENCY_LEN) - 1) << PSRAM_UHS_REG_UHS_LATENCY_POS)
#define PSRAM_UHS_REG_UHS_LATENCY_UMSK       (~(((1U << PSRAM_UHS_REG_UHS_LATENCY_LEN) - 1) << PSRAM_UHS_REG_UHS_LATENCY_POS))
#define PSRAM_UHS_REG_UHS_DRIVE_ST           PSRAM_UHS_REG_UHS_DRIVE_ST
#define PSRAM_UHS_REG_UHS_DRIVE_ST_POS       (4U)
#define PSRAM_UHS_REG_UHS_DRIVE_ST_LEN       (4U)
#define PSRAM_UHS_REG_UHS_DRIVE_ST_MSK       (((1U << PSRAM_UHS_REG_UHS_DRIVE_ST_LEN) - 1) << PSRAM_UHS_REG_UHS_DRIVE_ST_POS)
#define PSRAM_UHS_REG_UHS_DRIVE_ST_UMSK      (~(((1U << PSRAM_UHS_REG_UHS_DRIVE_ST_LEN) - 1) << PSRAM_UHS_REG_UHS_DRIVE_ST_POS))
#define PSRAM_UHS_REG_UHS_BL_16              PSRAM_UHS_REG_UHS_BL_16
#define PSRAM_UHS_REG_UHS_BL_16_POS          (8U)
#define PSRAM_UHS_REG_UHS_BL_16_LEN          (1U)
#define PSRAM_UHS_REG_UHS_BL_16_MSK          (((1U << PSRAM_UHS_REG_UHS_BL_16_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_16_POS)
#define PSRAM_UHS_REG_UHS_BL_16_UMSK         (~(((1U << PSRAM_UHS_REG_UHS_BL_16_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_16_POS))
#define PSRAM_UHS_REG_UHS_BL_32              PSRAM_UHS_REG_UHS_BL_32
#define PSRAM_UHS_REG_UHS_BL_32_POS          (9U)
#define PSRAM_UHS_REG_UHS_BL_32_LEN          (1U)
#define PSRAM_UHS_REG_UHS_BL_32_MSK          (((1U << PSRAM_UHS_REG_UHS_BL_32_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_32_POS)
#define PSRAM_UHS_REG_UHS_BL_32_UMSK         (~(((1U << PSRAM_UHS_REG_UHS_BL_32_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_32_POS))
#define PSRAM_UHS_REG_UHS_BL_64              PSRAM_UHS_REG_UHS_BL_64
#define PSRAM_UHS_REG_UHS_BL_64_POS          (10U)
#define PSRAM_UHS_REG_UHS_BL_64_LEN          (1U)
#define PSRAM_UHS_REG_UHS_BL_64_MSK          (((1U << PSRAM_UHS_REG_UHS_BL_64_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_64_POS)
#define PSRAM_UHS_REG_UHS_BL_64_UMSK         (~(((1U << PSRAM_UHS_REG_UHS_BL_64_LEN) - 1) << PSRAM_UHS_REG_UHS_BL_64_POS))

/* 0x24 : UHS_psram_status */
#define PSRAM_UHS_UHS_PSRAM_STATUS_OFFSET (0x24)
#define PSRAM_UHS_STS_UHS_LATENCY         PSRAM_UHS_STS_UHS_LATENCY
#define PSRAM_UHS_STS_UHS_LATENCY_POS     (0U)
#define PSRAM_UHS_STS_UHS_LATENCY_LEN     (3U)
#define PSRAM_UHS_STS_UHS_LATENCY_MSK     (((1U << PSRAM_UHS_STS_UHS_LATENCY_LEN) - 1) << PSRAM_UHS_STS_UHS_LATENCY_POS)
#define PSRAM_UHS_STS_UHS_LATENCY_UMSK    (~(((1U << PSRAM_UHS_STS_UHS_LATENCY_LEN) - 1) << PSRAM_UHS_STS_UHS_LATENCY_POS))
#define PSRAM_UHS_STS_UHS_DRIVE_ST        PSRAM_UHS_STS_UHS_DRIVE_ST
#define PSRAM_UHS_STS_UHS_DRIVE_ST_POS    (4U)
#define PSRAM_UHS_STS_UHS_DRIVE_ST_LEN    (4U)
#define PSRAM_UHS_STS_UHS_DRIVE_ST_MSK    (((1U << PSRAM_UHS_STS_UHS_DRIVE_ST_LEN) - 1) << PSRAM_UHS_STS_UHS_DRIVE_ST_POS)
#define PSRAM_UHS_STS_UHS_DRIVE_ST_UMSK   (~(((1U << PSRAM_UHS_STS_UHS_DRIVE_ST_LEN) - 1) << PSRAM_UHS_STS_UHS_DRIVE_ST_POS))
#define PSRAM_UHS_STS_UHS_BL_16           PSRAM_UHS_STS_UHS_BL_16
#define PSRAM_UHS_STS_UHS_BL_16_POS       (8U)
#define PSRAM_UHS_STS_UHS_BL_16_LEN       (1U)
#define PSRAM_UHS_STS_UHS_BL_16_MSK       (((1U << PSRAM_UHS_STS_UHS_BL_16_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_16_POS)
#define PSRAM_UHS_STS_UHS_BL_16_UMSK      (~(((1U << PSRAM_UHS_STS_UHS_BL_16_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_16_POS))
#define PSRAM_UHS_STS_UHS_BL_32           PSRAM_UHS_STS_UHS_BL_32
#define PSRAM_UHS_STS_UHS_BL_32_POS       (9U)
#define PSRAM_UHS_STS_UHS_BL_32_LEN       (1U)
#define PSRAM_UHS_STS_UHS_BL_32_MSK       (((1U << PSRAM_UHS_STS_UHS_BL_32_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_32_POS)
#define PSRAM_UHS_STS_UHS_BL_32_UMSK      (~(((1U << PSRAM_UHS_STS_UHS_BL_32_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_32_POS))
#define PSRAM_UHS_STS_UHS_BL_64           PSRAM_UHS_STS_UHS_BL_64
#define PSRAM_UHS_STS_UHS_BL_64_POS       (10U)
#define PSRAM_UHS_STS_UHS_BL_64_LEN       (1U)
#define PSRAM_UHS_STS_UHS_BL_64_MSK       (((1U << PSRAM_UHS_STS_UHS_BL_64_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_64_POS)
#define PSRAM_UHS_STS_UHS_BL_64_UMSK      (~(((1U << PSRAM_UHS_STS_UHS_BL_64_LEN) - 1) << PSRAM_UHS_STS_UHS_BL_64_POS))

/* 0x30 : UHS_timing_ctrl */
#define PSRAM_UHS_UHS_TIMING_CTRL_OFFSET (0x30)
#define PSRAM_UHS_REG_TRC_CYCLE          PSRAM_UHS_REG_TRC_CYCLE
#define PSRAM_UHS_REG_TRC_CYCLE_POS      (0U)
#define PSRAM_UHS_REG_TRC_CYCLE_LEN      (8U)
#define PSRAM_UHS_REG_TRC_CYCLE_MSK      (((1U << PSRAM_UHS_REG_TRC_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TRC_CYCLE_POS)
#define PSRAM_UHS_REG_TRC_CYCLE_UMSK     (~(((1U << PSRAM_UHS_REG_TRC_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TRC_CYCLE_POS))
#define PSRAM_UHS_REG_TCPHR_CYCLE        PSRAM_UHS_REG_TCPHR_CYCLE
#define PSRAM_UHS_REG_TCPHR_CYCLE_POS    (8U)
#define PSRAM_UHS_REG_TCPHR_CYCLE_LEN    (8U)
#define PSRAM_UHS_REG_TCPHR_CYCLE_MSK    (((1U << PSRAM_UHS_REG_TCPHR_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TCPHR_CYCLE_POS)
#define PSRAM_UHS_REG_TCPHR_CYCLE_UMSK   (~(((1U << PSRAM_UHS_REG_TCPHR_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TCPHR_CYCLE_POS))
#define PSRAM_UHS_REG_TCPHW_CYCLE        PSRAM_UHS_REG_TCPHW_CYCLE
#define PSRAM_UHS_REG_TCPHW_CYCLE_POS    (16U)
#define PSRAM_UHS_REG_TCPHW_CYCLE_LEN    (8U)
#define PSRAM_UHS_REG_TCPHW_CYCLE_MSK    (((1U << PSRAM_UHS_REG_TCPHW_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TCPHW_CYCLE_POS)
#define PSRAM_UHS_REG_TCPHW_CYCLE_UMSK   (~(((1U << PSRAM_UHS_REG_TCPHW_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TCPHW_CYCLE_POS))
#define PSRAM_UHS_REG_TRFC_CYCLE         PSRAM_UHS_REG_TRFC_CYCLE
#define PSRAM_UHS_REG_TRFC_CYCLE_POS     (24U)
#define PSRAM_UHS_REG_TRFC_CYCLE_LEN     (8U)
#define PSRAM_UHS_REG_TRFC_CYCLE_MSK     (((1U << PSRAM_UHS_REG_TRFC_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TRFC_CYCLE_POS)
#define PSRAM_UHS_REG_TRFC_CYCLE_UMSK    (~(((1U << PSRAM_UHS_REG_TRFC_CYCLE_LEN) - 1) << PSRAM_UHS_REG_TRFC_CYCLE_POS))

/* 0x34 : UHS_rsvd_reg */
#define PSRAM_UHS_UHS_RSVD_REG_OFFSET (0x34)
#define PSRAM_UHS_REG_MR0_7           PSRAM_UHS_REG_MR0_7
#define PSRAM_UHS_REG_MR0_7_POS       (0U)
#define PSRAM_UHS_REG_MR0_7_LEN       (1U)
#define PSRAM_UHS_REG_MR0_7_MSK       (((1U << PSRAM_UHS_REG_MR0_7_LEN) - 1) << PSRAM_UHS_REG_MR0_7_POS)
#define PSRAM_UHS_REG_MR0_7_UMSK      (~(((1U << PSRAM_UHS_REG_MR0_7_LEN) - 1) << PSRAM_UHS_REG_MR0_7_POS))
#define PSRAM_UHS_REG_MR2_2_0         PSRAM_UHS_REG_MR2_2_0
#define PSRAM_UHS_REG_MR2_2_0_POS     (1U)
#define PSRAM_UHS_REG_MR2_2_0_LEN     (3U)
#define PSRAM_UHS_REG_MR2_2_0_MSK     (((1U << PSRAM_UHS_REG_MR2_2_0_LEN) - 1) << PSRAM_UHS_REG_MR2_2_0_POS)
#define PSRAM_UHS_REG_MR2_2_0_UMSK    (~(((1U << PSRAM_UHS_REG_MR2_2_0_LEN) - 1) << PSRAM_UHS_REG_MR2_2_0_POS))
#define PSRAM_UHS_REG_MR2_7_6         PSRAM_UHS_REG_MR2_7_6
#define PSRAM_UHS_REG_MR2_7_6_POS     (4U)
#define PSRAM_UHS_REG_MR2_7_6_LEN     (2U)
#define PSRAM_UHS_REG_MR2_7_6_MSK     (((1U << PSRAM_UHS_REG_MR2_7_6_LEN) - 1) << PSRAM_UHS_REG_MR2_7_6_POS)
#define PSRAM_UHS_REG_MR2_7_6_UMSK    (~(((1U << PSRAM_UHS_REG_MR2_7_6_LEN) - 1) << PSRAM_UHS_REG_MR2_7_6_POS))

/* 0xC0 : UHS_dbg_sel */
#define PSRAM_UHS_UHS_DBG_SEL_OFFSET     (0xC0)
#define PSRAM_UHS_REG_PSRAM_DBG_EN       PSRAM_UHS_REG_PSRAM_DBG_EN
#define PSRAM_UHS_REG_PSRAM_DBG_EN_POS   (0U)
#define PSRAM_UHS_REG_PSRAM_DBG_EN_LEN   (1U)
#define PSRAM_UHS_REG_PSRAM_DBG_EN_MSK   (((1U << PSRAM_UHS_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DBG_EN_POS)
#define PSRAM_UHS_REG_PSRAM_DBG_EN_UMSK  (~(((1U << PSRAM_UHS_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DBG_EN_POS))
#define PSRAM_UHS_REG_PSRAM_DBG_SEL      PSRAM_UHS_REG_PSRAM_DBG_SEL
#define PSRAM_UHS_REG_PSRAM_DBG_SEL_POS  (4U)
#define PSRAM_UHS_REG_PSRAM_DBG_SEL_LEN  (4U)
#define PSRAM_UHS_REG_PSRAM_DBG_SEL_MSK  (((1U << PSRAM_UHS_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DBG_SEL_POS)
#define PSRAM_UHS_REG_PSRAM_DBG_SEL_UMSK (~(((1U << PSRAM_UHS_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DBG_SEL_POS))

/* 0xF0 : UHS_dummy_reg */
#define PSRAM_UHS_UHS_DUMMY_REG_OFFSET     (0xF0)
#define PSRAM_UHS_REG_PSRAM_DUMMY_REG      PSRAM_UHS_REG_PSRAM_DUMMY_REG
#define PSRAM_UHS_REG_PSRAM_DUMMY_REG_POS  (0U)
#define PSRAM_UHS_REG_PSRAM_DUMMY_REG_LEN  (32U)
#define PSRAM_UHS_REG_PSRAM_DUMMY_REG_MSK  (((1U << PSRAM_UHS_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DUMMY_REG_POS)
#define PSRAM_UHS_REG_PSRAM_DUMMY_REG_UMSK (~(((1U << PSRAM_UHS_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_UHS_REG_PSRAM_DUMMY_REG_POS))

/* 0x100 : phy_cfg_00 */
#define PSRAM_UHS_PHY_CFG_00_OFFSET  (0x100)
#define PSRAM_UHS_DQS_RDY            PSRAM_UHS_DQS_RDY
#define PSRAM_UHS_DQS_RDY_POS        (0U)
#define PSRAM_UHS_DQS_RDY_LEN        (1U)
#define PSRAM_UHS_DQS_RDY_MSK        (((1U << PSRAM_UHS_DQS_RDY_LEN) - 1) << PSRAM_UHS_DQS_RDY_POS)
#define PSRAM_UHS_DQS_RDY_UMSK       (~(((1U << PSRAM_UHS_DQS_RDY_LEN) - 1) << PSRAM_UHS_DQS_RDY_POS))
#define PSRAM_UHS_CK_SR              PSRAM_UHS_CK_SR
#define PSRAM_UHS_CK_SR_POS          (8U)
#define PSRAM_UHS_CK_SR_LEN          (2U)
#define PSRAM_UHS_CK_SR_MSK          (((1U << PSRAM_UHS_CK_SR_LEN) - 1) << PSRAM_UHS_CK_SR_POS)
#define PSRAM_UHS_CK_SR_UMSK         (~(((1U << PSRAM_UHS_CK_SR_LEN) - 1) << PSRAM_UHS_CK_SR_POS))
#define PSRAM_UHS_CLK0_POLARITY      PSRAM_UHS_CLK0_POLARITY
#define PSRAM_UHS_CLK0_POLARITY_POS  (15U)
#define PSRAM_UHS_CLK0_POLARITY_LEN  (1U)
#define PSRAM_UHS_CLK0_POLARITY_MSK  (((1U << PSRAM_UHS_CLK0_POLARITY_LEN) - 1) << PSRAM_UHS_CLK0_POLARITY_POS)
#define PSRAM_UHS_CLK0_POLARITY_UMSK (~(((1U << PSRAM_UHS_CLK0_POLARITY_LEN) - 1) << PSRAM_UHS_CLK0_POLARITY_POS))
#define PSRAM_UHS_CK_DLY_DRV         PSRAM_UHS_CK_DLY_DRV
#define PSRAM_UHS_CK_DLY_DRV_POS     (16U)
#define PSRAM_UHS_CK_DLY_DRV_LEN     (4U)
#define PSRAM_UHS_CK_DLY_DRV_MSK     (((1U << PSRAM_UHS_CK_DLY_DRV_LEN) - 1) << PSRAM_UHS_CK_DLY_DRV_POS)
#define PSRAM_UHS_CK_DLY_DRV_UMSK    (~(((1U << PSRAM_UHS_CK_DLY_DRV_LEN) - 1) << PSRAM_UHS_CK_DLY_DRV_POS))
#define PSRAM_UHS_CEN_SR             PSRAM_UHS_CEN_SR
#define PSRAM_UHS_CEN_SR_POS         (20U)
#define PSRAM_UHS_CEN_SR_LEN         (2U)
#define PSRAM_UHS_CEN_SR_MSK         (((1U << PSRAM_UHS_CEN_SR_LEN) - 1) << PSRAM_UHS_CEN_SR_POS)
#define PSRAM_UHS_CEN_SR_UMSK        (~(((1U << PSRAM_UHS_CEN_SR_LEN) - 1) << PSRAM_UHS_CEN_SR_POS))
#define PSRAM_UHS_CEN_DLY_DRV        PSRAM_UHS_CEN_DLY_DRV
#define PSRAM_UHS_CEN_DLY_DRV_POS    (28U)
#define PSRAM_UHS_CEN_DLY_DRV_LEN    (4U)
#define PSRAM_UHS_CEN_DLY_DRV_MSK    (((1U << PSRAM_UHS_CEN_DLY_DRV_LEN) - 1) << PSRAM_UHS_CEN_DLY_DRV_POS)
#define PSRAM_UHS_CEN_DLY_DRV_UMSK   (~(((1U << PSRAM_UHS_CEN_DLY_DRV_LEN) - 1) << PSRAM_UHS_CEN_DLY_DRV_POS))

/* 0x104 : phy_cfg_04 */
#define PSRAM_UHS_PHY_CFG_04_OFFSET (0x104)
#define PSRAM_UHS_DM1_SR            PSRAM_UHS_DM1_SR
#define PSRAM_UHS_DM1_SR_POS        (4U)
#define PSRAM_UHS_DM1_SR_LEN        (2U)
#define PSRAM_UHS_DM1_SR_MSK        (((1U << PSRAM_UHS_DM1_SR_LEN) - 1) << PSRAM_UHS_DM1_SR_POS)
#define PSRAM_UHS_DM1_SR_UMSK       (~(((1U << PSRAM_UHS_DM1_SR_LEN) - 1) << PSRAM_UHS_DM1_SR_POS))
#define PSRAM_UHS_DM1_DLY_DRV       PSRAM_UHS_DM1_DLY_DRV
#define PSRAM_UHS_DM1_DLY_DRV_POS   (12U)
#define PSRAM_UHS_DM1_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DM1_DLY_DRV_MSK   (((1U << PSRAM_UHS_DM1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DM1_DLY_DRV_POS)
#define PSRAM_UHS_DM1_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DM1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DM1_DLY_DRV_POS))
#define PSRAM_UHS_DM0_SR            PSRAM_UHS_DM0_SR
#define PSRAM_UHS_DM0_SR_POS        (20U)
#define PSRAM_UHS_DM0_SR_LEN        (2U)
#define PSRAM_UHS_DM0_SR_MSK        (((1U << PSRAM_UHS_DM0_SR_LEN) - 1) << PSRAM_UHS_DM0_SR_POS)
#define PSRAM_UHS_DM0_SR_UMSK       (~(((1U << PSRAM_UHS_DM0_SR_LEN) - 1) << PSRAM_UHS_DM0_SR_POS))
#define PSRAM_UHS_DM0_DLY_DRV       PSRAM_UHS_DM0_DLY_DRV
#define PSRAM_UHS_DM0_DLY_DRV_POS   (28U)
#define PSRAM_UHS_DM0_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DM0_DLY_DRV_MSK   (((1U << PSRAM_UHS_DM0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DM0_DLY_DRV_POS)
#define PSRAM_UHS_DM0_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DM0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DM0_DLY_DRV_POS))

/* 0x108 : phy_cfg_08 */
#define PSRAM_UHS_PHY_CFG_08_OFFSET (0x108)
#define PSRAM_UHS_DQ1_SR            PSRAM_UHS_DQ1_SR
#define PSRAM_UHS_DQ1_SR_POS        (0U)
#define PSRAM_UHS_DQ1_SR_LEN        (2U)
#define PSRAM_UHS_DQ1_SR_MSK        (((1U << PSRAM_UHS_DQ1_SR_LEN) - 1) << PSRAM_UHS_DQ1_SR_POS)
#define PSRAM_UHS_DQ1_SR_UMSK       (~(((1U << PSRAM_UHS_DQ1_SR_LEN) - 1) << PSRAM_UHS_DQ1_SR_POS))
#define PSRAM_UHS_DQ1_DLY_RX        PSRAM_UHS_DQ1_DLY_RX
#define PSRAM_UHS_DQ1_DLY_RX_POS    (8U)
#define PSRAM_UHS_DQ1_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ1_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ1_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ1_DLY_RX_POS)
#define PSRAM_UHS_DQ1_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ1_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ1_DLY_RX_POS))
#define PSRAM_UHS_DQ1_DLY_DRV       PSRAM_UHS_DQ1_DLY_DRV
#define PSRAM_UHS_DQ1_DLY_DRV_POS   (12U)
#define PSRAM_UHS_DQ1_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ1_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ1_DLY_DRV_POS)
#define PSRAM_UHS_DQ1_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ1_DLY_DRV_POS))
#define PSRAM_UHS_DQ0_SR            PSRAM_UHS_DQ0_SR
#define PSRAM_UHS_DQ0_SR_POS        (16U)
#define PSRAM_UHS_DQ0_SR_LEN        (2U)
#define PSRAM_UHS_DQ0_SR_MSK        (((1U << PSRAM_UHS_DQ0_SR_LEN) - 1) << PSRAM_UHS_DQ0_SR_POS)
#define PSRAM_UHS_DQ0_SR_UMSK       (~(((1U << PSRAM_UHS_DQ0_SR_LEN) - 1) << PSRAM_UHS_DQ0_SR_POS))
#define PSRAM_UHS_DQ0_DLY_RX        PSRAM_UHS_DQ0_DLY_RX
#define PSRAM_UHS_DQ0_DLY_RX_POS    (24U)
#define PSRAM_UHS_DQ0_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ0_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ0_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ0_DLY_RX_POS)
#define PSRAM_UHS_DQ0_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ0_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ0_DLY_RX_POS))
#define PSRAM_UHS_DQ0_DLY_DRV       PSRAM_UHS_DQ0_DLY_DRV
#define PSRAM_UHS_DQ0_DLY_DRV_POS   (28U)
#define PSRAM_UHS_DQ0_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ0_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ0_DLY_DRV_POS)
#define PSRAM_UHS_DQ0_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ0_DLY_DRV_POS))

/* 0x10C : phy_cfg_0C */
#define PSRAM_UHS_PHY_CFG_0C_OFFSET (0x10C)
#define PSRAM_UHS_DQ3_SR            PSRAM_UHS_DQ3_SR
#define PSRAM_UHS_DQ3_SR_POS        (0U)
#define PSRAM_UHS_DQ3_SR_LEN        (2U)
#define PSRAM_UHS_DQ3_SR_MSK        (((1U << PSRAM_UHS_DQ3_SR_LEN) - 1) << PSRAM_UHS_DQ3_SR_POS)
#define PSRAM_UHS_DQ3_SR_UMSK       (~(((1U << PSRAM_UHS_DQ3_SR_LEN) - 1) << PSRAM_UHS_DQ3_SR_POS))
#define PSRAM_UHS_DQ3_DLY_RX        PSRAM_UHS_DQ3_DLY_RX
#define PSRAM_UHS_DQ3_DLY_RX_POS    (8U)
#define PSRAM_UHS_DQ3_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ3_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ3_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ3_DLY_RX_POS)
#define PSRAM_UHS_DQ3_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ3_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ3_DLY_RX_POS))
#define PSRAM_UHS_DQ3_DLY_DRV       PSRAM_UHS_DQ3_DLY_DRV
#define PSRAM_UHS_DQ3_DLY_DRV_POS   (12U)
#define PSRAM_UHS_DQ3_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ3_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ3_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ3_DLY_DRV_POS)
#define PSRAM_UHS_DQ3_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ3_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ3_DLY_DRV_POS))
#define PSRAM_UHS_DQ2_SR            PSRAM_UHS_DQ2_SR
#define PSRAM_UHS_DQ2_SR_POS        (16U)
#define PSRAM_UHS_DQ2_SR_LEN        (2U)
#define PSRAM_UHS_DQ2_SR_MSK        (((1U << PSRAM_UHS_DQ2_SR_LEN) - 1) << PSRAM_UHS_DQ2_SR_POS)
#define PSRAM_UHS_DQ2_SR_UMSK       (~(((1U << PSRAM_UHS_DQ2_SR_LEN) - 1) << PSRAM_UHS_DQ2_SR_POS))
#define PSRAM_UHS_DQ2_DLY_RX        PSRAM_UHS_DQ2_DLY_RX
#define PSRAM_UHS_DQ2_DLY_RX_POS    (24U)
#define PSRAM_UHS_DQ2_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ2_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ2_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ2_DLY_RX_POS)
#define PSRAM_UHS_DQ2_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ2_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ2_DLY_RX_POS))
#define PSRAM_UHS_DQ2_DLY_DRV       PSRAM_UHS_DQ2_DLY_DRV
#define PSRAM_UHS_DQ2_DLY_DRV_POS   (28U)
#define PSRAM_UHS_DQ2_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ2_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ2_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ2_DLY_DRV_POS)
#define PSRAM_UHS_DQ2_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ2_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ2_DLY_DRV_POS))

/* 0x110 : phy_cfg_10 */
#define PSRAM_UHS_PHY_CFG_10_OFFSET (0x110)
#define PSRAM_UHS_DQ5_SR            PSRAM_UHS_DQ5_SR
#define PSRAM_UHS_DQ5_SR_POS        (0U)
#define PSRAM_UHS_DQ5_SR_LEN        (2U)
#define PSRAM_UHS_DQ5_SR_MSK        (((1U << PSRAM_UHS_DQ5_SR_LEN) - 1) << PSRAM_UHS_DQ5_SR_POS)
#define PSRAM_UHS_DQ5_SR_UMSK       (~(((1U << PSRAM_UHS_DQ5_SR_LEN) - 1) << PSRAM_UHS_DQ5_SR_POS))
#define PSRAM_UHS_DQ5_DLY_RX        PSRAM_UHS_DQ5_DLY_RX
#define PSRAM_UHS_DQ5_DLY_RX_POS    (8U)
#define PSRAM_UHS_DQ5_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ5_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ5_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ5_DLY_RX_POS)
#define PSRAM_UHS_DQ5_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ5_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ5_DLY_RX_POS))
#define PSRAM_UHS_DQ5_DLY_DRV       PSRAM_UHS_DQ5_DLY_DRV
#define PSRAM_UHS_DQ5_DLY_DRV_POS   (12U)
#define PSRAM_UHS_DQ5_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ5_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ5_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ5_DLY_DRV_POS)
#define PSRAM_UHS_DQ5_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ5_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ5_DLY_DRV_POS))
#define PSRAM_UHS_DQ4_SR            PSRAM_UHS_DQ4_SR
#define PSRAM_UHS_DQ4_SR_POS        (16U)
#define PSRAM_UHS_DQ4_SR_LEN        (2U)
#define PSRAM_UHS_DQ4_SR_MSK        (((1U << PSRAM_UHS_DQ4_SR_LEN) - 1) << PSRAM_UHS_DQ4_SR_POS)
#define PSRAM_UHS_DQ4_SR_UMSK       (~(((1U << PSRAM_UHS_DQ4_SR_LEN) - 1) << PSRAM_UHS_DQ4_SR_POS))
#define PSRAM_UHS_DQ4_DLY_RX        PSRAM_UHS_DQ4_DLY_RX
#define PSRAM_UHS_DQ4_DLY_RX_POS    (24U)
#define PSRAM_UHS_DQ4_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ4_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ4_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ4_DLY_RX_POS)
#define PSRAM_UHS_DQ4_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ4_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ4_DLY_RX_POS))
#define PSRAM_UHS_DQ4_DLY_DRV       PSRAM_UHS_DQ4_DLY_DRV
#define PSRAM_UHS_DQ4_DLY_DRV_POS   (28U)
#define PSRAM_UHS_DQ4_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ4_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ4_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ4_DLY_DRV_POS)
#define PSRAM_UHS_DQ4_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ4_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ4_DLY_DRV_POS))

/* 0x114 : phy_cfg_14 */
#define PSRAM_UHS_PHY_CFG_14_OFFSET (0x114)
#define PSRAM_UHS_DQ7_SR            PSRAM_UHS_DQ7_SR
#define PSRAM_UHS_DQ7_SR_POS        (0U)
#define PSRAM_UHS_DQ7_SR_LEN        (2U)
#define PSRAM_UHS_DQ7_SR_MSK        (((1U << PSRAM_UHS_DQ7_SR_LEN) - 1) << PSRAM_UHS_DQ7_SR_POS)
#define PSRAM_UHS_DQ7_SR_UMSK       (~(((1U << PSRAM_UHS_DQ7_SR_LEN) - 1) << PSRAM_UHS_DQ7_SR_POS))
#define PSRAM_UHS_DQ7_DLY_RX        PSRAM_UHS_DQ7_DLY_RX
#define PSRAM_UHS_DQ7_DLY_RX_POS    (8U)
#define PSRAM_UHS_DQ7_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ7_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ7_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ7_DLY_RX_POS)
#define PSRAM_UHS_DQ7_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ7_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ7_DLY_RX_POS))
#define PSRAM_UHS_DQ7_DLY_DRV       PSRAM_UHS_DQ7_DLY_DRV
#define PSRAM_UHS_DQ7_DLY_DRV_POS   (12U)
#define PSRAM_UHS_DQ7_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ7_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ7_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ7_DLY_DRV_POS)
#define PSRAM_UHS_DQ7_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ7_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ7_DLY_DRV_POS))
#define PSRAM_UHS_DQ6_SR            PSRAM_UHS_DQ6_SR
#define PSRAM_UHS_DQ6_SR_POS        (16U)
#define PSRAM_UHS_DQ6_SR_LEN        (2U)
#define PSRAM_UHS_DQ6_SR_MSK        (((1U << PSRAM_UHS_DQ6_SR_LEN) - 1) << PSRAM_UHS_DQ6_SR_POS)
#define PSRAM_UHS_DQ6_SR_UMSK       (~(((1U << PSRAM_UHS_DQ6_SR_LEN) - 1) << PSRAM_UHS_DQ6_SR_POS))
#define PSRAM_UHS_DQ6_DLY_RX        PSRAM_UHS_DQ6_DLY_RX
#define PSRAM_UHS_DQ6_DLY_RX_POS    (24U)
#define PSRAM_UHS_DQ6_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ6_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ6_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ6_DLY_RX_POS)
#define PSRAM_UHS_DQ6_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ6_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ6_DLY_RX_POS))
#define PSRAM_UHS_DQ6_DLY_DRV       PSRAM_UHS_DQ6_DLY_DRV
#define PSRAM_UHS_DQ6_DLY_DRV_POS   (28U)
#define PSRAM_UHS_DQ6_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ6_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ6_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ6_DLY_DRV_POS)
#define PSRAM_UHS_DQ6_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ6_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ6_DLY_DRV_POS))

/* 0x118 : phy_cfg_18 */
#define PSRAM_UHS_PHY_CFG_18_OFFSET (0x118)
#define PSRAM_UHS_DQ9_SR            PSRAM_UHS_DQ9_SR
#define PSRAM_UHS_DQ9_SR_POS        (0U)
#define PSRAM_UHS_DQ9_SR_LEN        (2U)
#define PSRAM_UHS_DQ9_SR_MSK        (((1U << PSRAM_UHS_DQ9_SR_LEN) - 1) << PSRAM_UHS_DQ9_SR_POS)
#define PSRAM_UHS_DQ9_SR_UMSK       (~(((1U << PSRAM_UHS_DQ9_SR_LEN) - 1) << PSRAM_UHS_DQ9_SR_POS))
#define PSRAM_UHS_DQ9_DLY_RX        PSRAM_UHS_DQ9_DLY_RX
#define PSRAM_UHS_DQ9_DLY_RX_POS    (8U)
#define PSRAM_UHS_DQ9_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ9_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ9_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ9_DLY_RX_POS)
#define PSRAM_UHS_DQ9_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ9_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ9_DLY_RX_POS))
#define PSRAM_UHS_DQ9_DLY_DRV       PSRAM_UHS_DQ9_DLY_DRV
#define PSRAM_UHS_DQ9_DLY_DRV_POS   (12U)
#define PSRAM_UHS_DQ9_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ9_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ9_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ9_DLY_DRV_POS)
#define PSRAM_UHS_DQ9_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ9_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ9_DLY_DRV_POS))
#define PSRAM_UHS_DQ8_SR            PSRAM_UHS_DQ8_SR
#define PSRAM_UHS_DQ8_SR_POS        (16U)
#define PSRAM_UHS_DQ8_SR_LEN        (2U)
#define PSRAM_UHS_DQ8_SR_MSK        (((1U << PSRAM_UHS_DQ8_SR_LEN) - 1) << PSRAM_UHS_DQ8_SR_POS)
#define PSRAM_UHS_DQ8_SR_UMSK       (~(((1U << PSRAM_UHS_DQ8_SR_LEN) - 1) << PSRAM_UHS_DQ8_SR_POS))
#define PSRAM_UHS_DQ8_DLY_RX        PSRAM_UHS_DQ8_DLY_RX
#define PSRAM_UHS_DQ8_DLY_RX_POS    (24U)
#define PSRAM_UHS_DQ8_DLY_RX_LEN    (4U)
#define PSRAM_UHS_DQ8_DLY_RX_MSK    (((1U << PSRAM_UHS_DQ8_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ8_DLY_RX_POS)
#define PSRAM_UHS_DQ8_DLY_RX_UMSK   (~(((1U << PSRAM_UHS_DQ8_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ8_DLY_RX_POS))
#define PSRAM_UHS_DQ8_DLY_DRV       PSRAM_UHS_DQ8_DLY_DRV
#define PSRAM_UHS_DQ8_DLY_DRV_POS   (28U)
#define PSRAM_UHS_DQ8_DLY_DRV_LEN   (4U)
#define PSRAM_UHS_DQ8_DLY_DRV_MSK   (((1U << PSRAM_UHS_DQ8_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ8_DLY_DRV_POS)
#define PSRAM_UHS_DQ8_DLY_DRV_UMSK  (~(((1U << PSRAM_UHS_DQ8_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ8_DLY_DRV_POS))

/* 0x11C : phy_cfg_1C */
#define PSRAM_UHS_PHY_CFG_1C_OFFSET (0x11C)
#define PSRAM_UHS_DQ11_SR           PSRAM_UHS_DQ11_SR
#define PSRAM_UHS_DQ11_SR_POS       (0U)
#define PSRAM_UHS_DQ11_SR_LEN       (2U)
#define PSRAM_UHS_DQ11_SR_MSK       (((1U << PSRAM_UHS_DQ11_SR_LEN) - 1) << PSRAM_UHS_DQ11_SR_POS)
#define PSRAM_UHS_DQ11_SR_UMSK      (~(((1U << PSRAM_UHS_DQ11_SR_LEN) - 1) << PSRAM_UHS_DQ11_SR_POS))
#define PSRAM_UHS_DQ11_DLY_RX       PSRAM_UHS_DQ11_DLY_RX
#define PSRAM_UHS_DQ11_DLY_RX_POS   (8U)
#define PSRAM_UHS_DQ11_DLY_RX_LEN   (4U)
#define PSRAM_UHS_DQ11_DLY_RX_MSK   (((1U << PSRAM_UHS_DQ11_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ11_DLY_RX_POS)
#define PSRAM_UHS_DQ11_DLY_RX_UMSK  (~(((1U << PSRAM_UHS_DQ11_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ11_DLY_RX_POS))
#define PSRAM_UHS_DQ11_DLY_DRV      PSRAM_UHS_DQ11_DLY_DRV
#define PSRAM_UHS_DQ11_DLY_DRV_POS  (12U)
#define PSRAM_UHS_DQ11_DLY_DRV_LEN  (4U)
#define PSRAM_UHS_DQ11_DLY_DRV_MSK  (((1U << PSRAM_UHS_DQ11_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ11_DLY_DRV_POS)
#define PSRAM_UHS_DQ11_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ11_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ11_DLY_DRV_POS))
#define PSRAM_UHS_DQ10_SR           PSRAM_UHS_DQ10_SR
#define PSRAM_UHS_DQ10_SR_POS       (16U)
#define PSRAM_UHS_DQ10_SR_LEN       (2U)
#define PSRAM_UHS_DQ10_SR_MSK       (((1U << PSRAM_UHS_DQ10_SR_LEN) - 1) << PSRAM_UHS_DQ10_SR_POS)
#define PSRAM_UHS_DQ10_SR_UMSK      (~(((1U << PSRAM_UHS_DQ10_SR_LEN) - 1) << PSRAM_UHS_DQ10_SR_POS))
#define PSRAM_UHS_DQ10_DLY_RX       PSRAM_UHS_DQ10_DLY_RX
#define PSRAM_UHS_DQ10_DLY_RX_POS   (24U)
#define PSRAM_UHS_DQ10_DLY_RX_LEN   (4U)
#define PSRAM_UHS_DQ10_DLY_RX_MSK   (((1U << PSRAM_UHS_DQ10_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ10_DLY_RX_POS)
#define PSRAM_UHS_DQ10_DLY_RX_UMSK  (~(((1U << PSRAM_UHS_DQ10_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ10_DLY_RX_POS))
#define PSRAM_UHS_DQ10_DLY_DRV      PSRAM_UHS_DQ10_DLY_DRV
#define PSRAM_UHS_DQ10_DLY_DRV_POS  (28U)
#define PSRAM_UHS_DQ10_DLY_DRV_LEN  (4U)
#define PSRAM_UHS_DQ10_DLY_DRV_MSK  (((1U << PSRAM_UHS_DQ10_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ10_DLY_DRV_POS)
#define PSRAM_UHS_DQ10_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ10_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ10_DLY_DRV_POS))

/* 0x120 : phy_cfg_20 */
#define PSRAM_UHS_PHY_CFG_20_OFFSET (0x120)
#define PSRAM_UHS_DQ13_SR           PSRAM_UHS_DQ13_SR
#define PSRAM_UHS_DQ13_SR_POS       (0U)
#define PSRAM_UHS_DQ13_SR_LEN       (2U)
#define PSRAM_UHS_DQ13_SR_MSK       (((1U << PSRAM_UHS_DQ13_SR_LEN) - 1) << PSRAM_UHS_DQ13_SR_POS)
#define PSRAM_UHS_DQ13_SR_UMSK      (~(((1U << PSRAM_UHS_DQ13_SR_LEN) - 1) << PSRAM_UHS_DQ13_SR_POS))
#define PSRAM_UHS_DQ13_DLY_RX       PSRAM_UHS_DQ13_DLY_RX
#define PSRAM_UHS_DQ13_DLY_RX_POS   (8U)
#define PSRAM_UHS_DQ13_DLY_RX_LEN   (4U)
#define PSRAM_UHS_DQ13_DLY_RX_MSK   (((1U << PSRAM_UHS_DQ13_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ13_DLY_RX_POS)
#define PSRAM_UHS_DQ13_DLY_RX_UMSK  (~(((1U << PSRAM_UHS_DQ13_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ13_DLY_RX_POS))
#define PSRAM_UHS_DQ13_DLY_DRV      PSRAM_UHS_DQ13_DLY_DRV
#define PSRAM_UHS_DQ13_DLY_DRV_POS  (12U)
#define PSRAM_UHS_DQ13_DLY_DRV_LEN  (4U)
#define PSRAM_UHS_DQ13_DLY_DRV_MSK  (((1U << PSRAM_UHS_DQ13_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ13_DLY_DRV_POS)
#define PSRAM_UHS_DQ13_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ13_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ13_DLY_DRV_POS))
#define PSRAM_UHS_DQ12_SR           PSRAM_UHS_DQ12_SR
#define PSRAM_UHS_DQ12_SR_POS       (16U)
#define PSRAM_UHS_DQ12_SR_LEN       (2U)
#define PSRAM_UHS_DQ12_SR_MSK       (((1U << PSRAM_UHS_DQ12_SR_LEN) - 1) << PSRAM_UHS_DQ12_SR_POS)
#define PSRAM_UHS_DQ12_SR_UMSK      (~(((1U << PSRAM_UHS_DQ12_SR_LEN) - 1) << PSRAM_UHS_DQ12_SR_POS))
#define PSRAM_UHS_DQ12_DLY_RX       PSRAM_UHS_DQ12_DLY_RX
#define PSRAM_UHS_DQ12_DLY_RX_POS   (24U)
#define PSRAM_UHS_DQ12_DLY_RX_LEN   (4U)
#define PSRAM_UHS_DQ12_DLY_RX_MSK   (((1U << PSRAM_UHS_DQ12_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ12_DLY_RX_POS)
#define PSRAM_UHS_DQ12_DLY_RX_UMSK  (~(((1U << PSRAM_UHS_DQ12_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ12_DLY_RX_POS))
#define PSRAM_UHS_DQ12_DLY_DRV      PSRAM_UHS_DQ12_DLY_DRV
#define PSRAM_UHS_DQ12_DLY_DRV_POS  (28U)
#define PSRAM_UHS_DQ12_DLY_DRV_LEN  (4U)
#define PSRAM_UHS_DQ12_DLY_DRV_MSK  (((1U << PSRAM_UHS_DQ12_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ12_DLY_DRV_POS)
#define PSRAM_UHS_DQ12_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ12_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ12_DLY_DRV_POS))

/* 0x124 : phy_cfg_24 */
#define PSRAM_UHS_PHY_CFG_24_OFFSET (0x124)
#define PSRAM_UHS_DQ15_SR           PSRAM_UHS_DQ15_SR
#define PSRAM_UHS_DQ15_SR_POS       (0U)
#define PSRAM_UHS_DQ15_SR_LEN       (2U)
#define PSRAM_UHS_DQ15_SR_MSK       (((1U << PSRAM_UHS_DQ15_SR_LEN) - 1) << PSRAM_UHS_DQ15_SR_POS)
#define PSRAM_UHS_DQ15_SR_UMSK      (~(((1U << PSRAM_UHS_DQ15_SR_LEN) - 1) << PSRAM_UHS_DQ15_SR_POS))
#define PSRAM_UHS_DQ15_DLY_RX       PSRAM_UHS_DQ15_DLY_RX
#define PSRAM_UHS_DQ15_DLY_RX_POS   (8U)
#define PSRAM_UHS_DQ15_DLY_RX_LEN   (4U)
#define PSRAM_UHS_DQ15_DLY_RX_MSK   (((1U << PSRAM_UHS_DQ15_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ15_DLY_RX_POS)
#define PSRAM_UHS_DQ15_DLY_RX_UMSK  (~(((1U << PSRAM_UHS_DQ15_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ15_DLY_RX_POS))
#define PSRAM_UHS_DQ15_DLY_DRV      PSRAM_UHS_DQ15_DLY_DRV
#define PSRAM_UHS_DQ15_DLY_DRV_POS  (12U)
#define PSRAM_UHS_DQ15_DLY_DRV_LEN  (4U)
#define PSRAM_UHS_DQ15_DLY_DRV_MSK  (((1U << PSRAM_UHS_DQ15_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ15_DLY_DRV_POS)
#define PSRAM_UHS_DQ15_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ15_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ15_DLY_DRV_POS))
#define PSRAM_UHS_DQ14_SR           PSRAM_UHS_DQ14_SR
#define PSRAM_UHS_DQ14_SR_POS       (16U)
#define PSRAM_UHS_DQ14_SR_LEN       (2U)
#define PSRAM_UHS_DQ14_SR_MSK       (((1U << PSRAM_UHS_DQ14_SR_LEN) - 1) << PSRAM_UHS_DQ14_SR_POS)
#define PSRAM_UHS_DQ14_SR_UMSK      (~(((1U << PSRAM_UHS_DQ14_SR_LEN) - 1) << PSRAM_UHS_DQ14_SR_POS))
#define PSRAM_UHS_DQ14_DLY_RX       PSRAM_UHS_DQ14_DLY_RX
#define PSRAM_UHS_DQ14_DLY_RX_POS   (24U)
#define PSRAM_UHS_DQ14_DLY_RX_LEN   (4U)
#define PSRAM_UHS_DQ14_DLY_RX_MSK   (((1U << PSRAM_UHS_DQ14_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ14_DLY_RX_POS)
#define PSRAM_UHS_DQ14_DLY_RX_UMSK  (~(((1U << PSRAM_UHS_DQ14_DLY_RX_LEN) - 1) << PSRAM_UHS_DQ14_DLY_RX_POS))
#define PSRAM_UHS_DQ14_DLY_DRV      PSRAM_UHS_DQ14_DLY_DRV
#define PSRAM_UHS_DQ14_DLY_DRV_POS  (28U)
#define PSRAM_UHS_DQ14_DLY_DRV_LEN  (4U)
#define PSRAM_UHS_DQ14_DLY_DRV_MSK  (((1U << PSRAM_UHS_DQ14_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ14_DLY_DRV_POS)
#define PSRAM_UHS_DQ14_DLY_DRV_UMSK (~(((1U << PSRAM_UHS_DQ14_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQ14_DLY_DRV_POS))

/* 0x128 : phy_cfg_28 */
#define PSRAM_UHS_PHY_CFG_28_OFFSET     (0x128)
#define PSRAM_UHS_DQS0N_DLY_RX          PSRAM_UHS_DQS0N_DLY_RX
#define PSRAM_UHS_DQS0N_DLY_RX_POS      (8U)
#define PSRAM_UHS_DQS0N_DLY_RX_LEN      (4U)
#define PSRAM_UHS_DQS0N_DLY_RX_MSK      (((1U << PSRAM_UHS_DQS0N_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0N_DLY_RX_POS)
#define PSRAM_UHS_DQS0N_DLY_RX_UMSK     (~(((1U << PSRAM_UHS_DQS0N_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0N_DLY_RX_POS))
#define PSRAM_UHS_DQS0_SR               PSRAM_UHS_DQS0_SR
#define PSRAM_UHS_DQS0_SR_POS           (12U)
#define PSRAM_UHS_DQS0_SR_LEN           (2U)
#define PSRAM_UHS_DQS0_SR_MSK           (((1U << PSRAM_UHS_DQS0_SR_LEN) - 1) << PSRAM_UHS_DQS0_SR_POS)
#define PSRAM_UHS_DQS0_SR_UMSK          (~(((1U << PSRAM_UHS_DQS0_SR_LEN) - 1) << PSRAM_UHS_DQS0_SR_POS))
#define PSRAM_UHS_DQS0_SEL              PSRAM_UHS_DQS0_SEL
#define PSRAM_UHS_DQS0_SEL_POS          (14U)
#define PSRAM_UHS_DQS0_SEL_LEN          (2U)
#define PSRAM_UHS_DQS0_SEL_MSK          (((1U << PSRAM_UHS_DQS0_SEL_LEN) - 1) << PSRAM_UHS_DQS0_SEL_POS)
#define PSRAM_UHS_DQS0_SEL_UMSK         (~(((1U << PSRAM_UHS_DQS0_SEL_LEN) - 1) << PSRAM_UHS_DQS0_SEL_POS))
#define PSRAM_UHS_DQS0_DLY_RX           PSRAM_UHS_DQS0_DLY_RX
#define PSRAM_UHS_DQS0_DLY_RX_POS       (20U)
#define PSRAM_UHS_DQS0_DLY_RX_LEN       (4U)
#define PSRAM_UHS_DQS0_DLY_RX_MSK       (((1U << PSRAM_UHS_DQS0_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0_DLY_RX_POS)
#define PSRAM_UHS_DQS0_DLY_RX_UMSK      (~(((1U << PSRAM_UHS_DQS0_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0_DLY_RX_POS))
#define PSRAM_UHS_DQS0_DLY_DRV          PSRAM_UHS_DQS0_DLY_DRV
#define PSRAM_UHS_DQS0_DLY_DRV_POS      (24U)
#define PSRAM_UHS_DQS0_DLY_DRV_LEN      (4U)
#define PSRAM_UHS_DQS0_DLY_DRV_MSK      (((1U << PSRAM_UHS_DQS0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQS0_DLY_DRV_POS)
#define PSRAM_UHS_DQS0_DLY_DRV_UMSK     (~(((1U << PSRAM_UHS_DQS0_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQS0_DLY_DRV_POS))
#define PSRAM_UHS_DQS0_DIFF_DLY_RX      PSRAM_UHS_DQS0_DIFF_DLY_RX
#define PSRAM_UHS_DQS0_DIFF_DLY_RX_POS  (28U)
#define PSRAM_UHS_DQS0_DIFF_DLY_RX_LEN  (4U)
#define PSRAM_UHS_DQS0_DIFF_DLY_RX_MSK  (((1U << PSRAM_UHS_DQS0_DIFF_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0_DIFF_DLY_RX_POS)
#define PSRAM_UHS_DQS0_DIFF_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQS0_DIFF_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS0_DIFF_DLY_RX_POS))

/* 0x12C : phy_cfg_2C */
#define PSRAM_UHS_PHY_CFG_2C_OFFSET     (0x12C)
#define PSRAM_UHS_IPP5UN_LPDDR          PSRAM_UHS_IPP5UN_LPDDR
#define PSRAM_UHS_IPP5UN_LPDDR_POS      (0U)
#define PSRAM_UHS_IPP5UN_LPDDR_LEN      (1U)
#define PSRAM_UHS_IPP5UN_LPDDR_MSK      (((1U << PSRAM_UHS_IPP5UN_LPDDR_LEN) - 1) << PSRAM_UHS_IPP5UN_LPDDR_POS)
#define PSRAM_UHS_IPP5UN_LPDDR_UMSK     (~(((1U << PSRAM_UHS_IPP5UN_LPDDR_LEN) - 1) << PSRAM_UHS_IPP5UN_LPDDR_POS))
#define PSRAM_UHS_EN_RX_FE              PSRAM_UHS_EN_RX_FE
#define PSRAM_UHS_EN_RX_FE_POS          (1U)
#define PSRAM_UHS_EN_RX_FE_LEN          (1U)
#define PSRAM_UHS_EN_RX_FE_MSK          (((1U << PSRAM_UHS_EN_RX_FE_LEN) - 1) << PSRAM_UHS_EN_RX_FE_POS)
#define PSRAM_UHS_EN_RX_FE_UMSK         (~(((1U << PSRAM_UHS_EN_RX_FE_LEN) - 1) << PSRAM_UHS_EN_RX_FE_POS))
#define PSRAM_UHS_EN_BIAS               PSRAM_UHS_EN_BIAS
#define PSRAM_UHS_EN_BIAS_POS           (2U)
#define PSRAM_UHS_EN_BIAS_LEN           (1U)
#define PSRAM_UHS_EN_BIAS_MSK           (((1U << PSRAM_UHS_EN_BIAS_LEN) - 1) << PSRAM_UHS_EN_BIAS_POS)
#define PSRAM_UHS_EN_BIAS_UMSK          (~(((1U << PSRAM_UHS_EN_BIAS_LEN) - 1) << PSRAM_UHS_EN_BIAS_POS))
#define PSRAM_UHS_DQS1N_DLY_RX          PSRAM_UHS_DQS1N_DLY_RX
#define PSRAM_UHS_DQS1N_DLY_RX_POS      (8U)
#define PSRAM_UHS_DQS1N_DLY_RX_LEN      (4U)
#define PSRAM_UHS_DQS1N_DLY_RX_MSK      (((1U << PSRAM_UHS_DQS1N_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1N_DLY_RX_POS)
#define PSRAM_UHS_DQS1N_DLY_RX_UMSK     (~(((1U << PSRAM_UHS_DQS1N_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1N_DLY_RX_POS))
#define PSRAM_UHS_DQS1_SR               PSRAM_UHS_DQS1_SR
#define PSRAM_UHS_DQS1_SR_POS           (12U)
#define PSRAM_UHS_DQS1_SR_LEN           (2U)
#define PSRAM_UHS_DQS1_SR_MSK           (((1U << PSRAM_UHS_DQS1_SR_LEN) - 1) << PSRAM_UHS_DQS1_SR_POS)
#define PSRAM_UHS_DQS1_SR_UMSK          (~(((1U << PSRAM_UHS_DQS1_SR_LEN) - 1) << PSRAM_UHS_DQS1_SR_POS))
#define PSRAM_UHS_DQS1_SEL              PSRAM_UHS_DQS1_SEL
#define PSRAM_UHS_DQS1_SEL_POS          (14U)
#define PSRAM_UHS_DQS1_SEL_LEN          (2U)
#define PSRAM_UHS_DQS1_SEL_MSK          (((1U << PSRAM_UHS_DQS1_SEL_LEN) - 1) << PSRAM_UHS_DQS1_SEL_POS)
#define PSRAM_UHS_DQS1_SEL_UMSK         (~(((1U << PSRAM_UHS_DQS1_SEL_LEN) - 1) << PSRAM_UHS_DQS1_SEL_POS))
#define PSRAM_UHS_DQS1_DLY_RX           PSRAM_UHS_DQS1_DLY_RX
#define PSRAM_UHS_DQS1_DLY_RX_POS       (20U)
#define PSRAM_UHS_DQS1_DLY_RX_LEN       (4U)
#define PSRAM_UHS_DQS1_DLY_RX_MSK       (((1U << PSRAM_UHS_DQS1_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1_DLY_RX_POS)
#define PSRAM_UHS_DQS1_DLY_RX_UMSK      (~(((1U << PSRAM_UHS_DQS1_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1_DLY_RX_POS))
#define PSRAM_UHS_DQS1_DLY_DRV          PSRAM_UHS_DQS1_DLY_DRV
#define PSRAM_UHS_DQS1_DLY_DRV_POS      (24U)
#define PSRAM_UHS_DQS1_DLY_DRV_LEN      (4U)
#define PSRAM_UHS_DQS1_DLY_DRV_MSK      (((1U << PSRAM_UHS_DQS1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQS1_DLY_DRV_POS)
#define PSRAM_UHS_DQS1_DLY_DRV_UMSK     (~(((1U << PSRAM_UHS_DQS1_DLY_DRV_LEN) - 1) << PSRAM_UHS_DQS1_DLY_DRV_POS))
#define PSRAM_UHS_DQS1_DIFF_DLY_RX      PSRAM_UHS_DQS1_DIFF_DLY_RX
#define PSRAM_UHS_DQS1_DIFF_DLY_RX_POS  (28U)
#define PSRAM_UHS_DQS1_DIFF_DLY_RX_LEN  (4U)
#define PSRAM_UHS_DQS1_DIFF_DLY_RX_MSK  (((1U << PSRAM_UHS_DQS1_DIFF_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1_DIFF_DLY_RX_POS)
#define PSRAM_UHS_DQS1_DIFF_DLY_RX_UMSK (~(((1U << PSRAM_UHS_DQS1_DIFF_DLY_RX_LEN) - 1) << PSRAM_UHS_DQS1_DIFF_DLY_RX_POS))

/* 0x130 : phy_cfg_30 */
#define PSRAM_UHS_PHY_CFG_30_OFFSET  (0x130)
#define PSRAM_UHS_PHY_WL_DQ_DIG      PSRAM_UHS_PHY_WL_DQ_DIG
#define PSRAM_UHS_PHY_WL_DQ_DIG_POS  (0U)
#define PSRAM_UHS_PHY_WL_DQ_DIG_LEN  (3U)
#define PSRAM_UHS_PHY_WL_DQ_DIG_MSK  (((1U << PSRAM_UHS_PHY_WL_DQ_DIG_LEN) - 1) << PSRAM_UHS_PHY_WL_DQ_DIG_POS)
#define PSRAM_UHS_PHY_WL_DQ_DIG_UMSK (~(((1U << PSRAM_UHS_PHY_WL_DQ_DIG_LEN) - 1) << PSRAM_UHS_PHY_WL_DQ_DIG_POS))
#define PSRAM_UHS_PHY_WL_DQ_ANA      PSRAM_UHS_PHY_WL_DQ_ANA
#define PSRAM_UHS_PHY_WL_DQ_ANA_POS  (4U)
#define PSRAM_UHS_PHY_WL_DQ_ANA_LEN  (3U)
#define PSRAM_UHS_PHY_WL_DQ_ANA_MSK  (((1U << PSRAM_UHS_PHY_WL_DQ_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_DQ_ANA_POS)
#define PSRAM_UHS_PHY_WL_DQ_ANA_UMSK (~(((1U << PSRAM_UHS_PHY_WL_DQ_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_DQ_ANA_POS))
#define PSRAM_UHS_PHY_WL_DIG         PSRAM_UHS_PHY_WL_DIG
#define PSRAM_UHS_PHY_WL_DIG_POS     (8U)
#define PSRAM_UHS_PHY_WL_DIG_LEN     (3U)
#define PSRAM_UHS_PHY_WL_DIG_MSK     (((1U << PSRAM_UHS_PHY_WL_DIG_LEN) - 1) << PSRAM_UHS_PHY_WL_DIG_POS)
#define PSRAM_UHS_PHY_WL_DIG_UMSK    (~(((1U << PSRAM_UHS_PHY_WL_DIG_LEN) - 1) << PSRAM_UHS_PHY_WL_DIG_POS))
#define PSRAM_UHS_PHY_WL_ANA         PSRAM_UHS_PHY_WL_ANA
#define PSRAM_UHS_PHY_WL_ANA_POS     (12U)
#define PSRAM_UHS_PHY_WL_ANA_LEN     (3U)
#define PSRAM_UHS_PHY_WL_ANA_MSK     (((1U << PSRAM_UHS_PHY_WL_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_ANA_POS)
#define PSRAM_UHS_PHY_WL_ANA_UMSK    (~(((1U << PSRAM_UHS_PHY_WL_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_ANA_POS))
#define PSRAM_UHS_PHY_RL_DIG         PSRAM_UHS_PHY_RL_DIG
#define PSRAM_UHS_PHY_RL_DIG_POS     (16U)
#define PSRAM_UHS_PHY_RL_DIG_LEN     (4U)
#define PSRAM_UHS_PHY_RL_DIG_MSK     (((1U << PSRAM_UHS_PHY_RL_DIG_LEN) - 1) << PSRAM_UHS_PHY_RL_DIG_POS)
#define PSRAM_UHS_PHY_RL_DIG_UMSK    (~(((1U << PSRAM_UHS_PHY_RL_DIG_LEN) - 1) << PSRAM_UHS_PHY_RL_DIG_POS))
#define PSRAM_UHS_PHY_RL_ANA         PSRAM_UHS_PHY_RL_ANA
#define PSRAM_UHS_PHY_RL_ANA_POS     (20U)
#define PSRAM_UHS_PHY_RL_ANA_LEN     (3U)
#define PSRAM_UHS_PHY_RL_ANA_MSK     (((1U << PSRAM_UHS_PHY_RL_ANA_LEN) - 1) << PSRAM_UHS_PHY_RL_ANA_POS)
#define PSRAM_UHS_PHY_RL_ANA_UMSK    (~(((1U << PSRAM_UHS_PHY_RL_ANA_LEN) - 1) << PSRAM_UHS_PHY_RL_ANA_POS))
#define PSRAM_UHS_OE_TIMER           PSRAM_UHS_OE_TIMER
#define PSRAM_UHS_OE_TIMER_POS       (24U)
#define PSRAM_UHS_OE_TIMER_LEN       (2U)
#define PSRAM_UHS_OE_TIMER_MSK       (((1U << PSRAM_UHS_OE_TIMER_LEN) - 1) << PSRAM_UHS_OE_TIMER_POS)
#define PSRAM_UHS_OE_TIMER_UMSK      (~(((1U << PSRAM_UHS_OE_TIMER_LEN) - 1) << PSRAM_UHS_OE_TIMER_POS))
#define PSRAM_UHS_VREF_MODE          PSRAM_UHS_VREF_MODE
#define PSRAM_UHS_VREF_MODE_POS      (26U)
#define PSRAM_UHS_VREF_MODE_LEN      (1U)
#define PSRAM_UHS_VREF_MODE_MSK      (((1U << PSRAM_UHS_VREF_MODE_LEN) - 1) << PSRAM_UHS_VREF_MODE_POS)
#define PSRAM_UHS_VREF_MODE_UMSK     (~(((1U << PSRAM_UHS_VREF_MODE_LEN) - 1) << PSRAM_UHS_VREF_MODE_POS))
#define PSRAM_UHS_OE_CTRL_HW         PSRAM_UHS_OE_CTRL_HW
#define PSRAM_UHS_OE_CTRL_HW_POS     (27U)
#define PSRAM_UHS_OE_CTRL_HW_LEN     (1U)
#define PSRAM_UHS_OE_CTRL_HW_MSK     (((1U << PSRAM_UHS_OE_CTRL_HW_LEN) - 1) << PSRAM_UHS_OE_CTRL_HW_POS)
#define PSRAM_UHS_OE_CTRL_HW_UMSK    (~(((1U << PSRAM_UHS_OE_CTRL_HW_LEN) - 1) << PSRAM_UHS_OE_CTRL_HW_POS))
#define PSRAM_UHS_ODT_SEL            PSRAM_UHS_ODT_SEL
#define PSRAM_UHS_ODT_SEL_POS        (28U)
#define PSRAM_UHS_ODT_SEL_LEN        (4U)
#define PSRAM_UHS_ODT_SEL_MSK        (((1U << PSRAM_UHS_ODT_SEL_LEN) - 1) << PSRAM_UHS_ODT_SEL_POS)
#define PSRAM_UHS_ODT_SEL_UMSK       (~(((1U << PSRAM_UHS_ODT_SEL_LEN) - 1) << PSRAM_UHS_ODT_SEL_POS))

/* 0x134 : phy_cfg_34 */
#define PSRAM_UHS_PHY_CFG_34_OFFSET             (0x134)
#define PSRAM_UHS_REG_TIMER_DQS_START           PSRAM_UHS_REG_TIMER_DQS_START
#define PSRAM_UHS_REG_TIMER_DQS_START_POS       (0U)
#define PSRAM_UHS_REG_TIMER_DQS_START_LEN       (8U)
#define PSRAM_UHS_REG_TIMER_DQS_START_MSK       (((1U << PSRAM_UHS_REG_TIMER_DQS_START_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_START_POS)
#define PSRAM_UHS_REG_TIMER_DQS_START_UMSK      (~(((1U << PSRAM_UHS_REG_TIMER_DQS_START_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_START_POS))
#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP      PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP
#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_POS  (8U)
#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_LEN  (8U)
#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_MSK  (((1U << PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_POS)
#define PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_ARRAY_STOP_POS))
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE         PSRAM_UHS_REG_TIMER_ARRAY_WRITE
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_POS     (16U)
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_LEN     (8U)
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_MSK     (((1U << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_POS)
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_UMSK    (~(((1U << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_POS))
#define PSRAM_UHS_REG_TIMER_ARRAY_READ          PSRAM_UHS_REG_TIMER_ARRAY_READ
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_POS      (24U)
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_LEN      (8U)
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_MSK      (((1U << PSRAM_UHS_REG_TIMER_ARRAY_READ_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_READ_POS)
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_UMSK     (~(((1U << PSRAM_UHS_REG_TIMER_ARRAY_READ_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_READ_POS))

/* 0x138 : phy_cfg_38 */
#define PSRAM_UHS_PHY_CFG_38_OFFSET           (0x138)
#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH      PSRAM_UHS_REG_TIMER_AUTO_REFRESH
#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH_POS  (0U)
#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH_LEN  (8U)
#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH_MSK  (((1U << PSRAM_UHS_REG_TIMER_AUTO_REFRESH_LEN) - 1) << PSRAM_UHS_REG_TIMER_AUTO_REFRESH_POS)
#define PSRAM_UHS_REG_TIMER_AUTO_REFRESH_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_AUTO_REFRESH_LEN) - 1) << PSRAM_UHS_REG_TIMER_AUTO_REFRESH_POS))
#define PSRAM_UHS_REG_TIMER_REG_WRITE         PSRAM_UHS_REG_TIMER_REG_WRITE
#define PSRAM_UHS_REG_TIMER_REG_WRITE_POS     (8U)
#define PSRAM_UHS_REG_TIMER_REG_WRITE_LEN     (8U)
#define PSRAM_UHS_REG_TIMER_REG_WRITE_MSK     (((1U << PSRAM_UHS_REG_TIMER_REG_WRITE_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_WRITE_POS)
#define PSRAM_UHS_REG_TIMER_REG_WRITE_UMSK    (~(((1U << PSRAM_UHS_REG_TIMER_REG_WRITE_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_WRITE_POS))
#define PSRAM_UHS_REG_TIMER_REG_READ          PSRAM_UHS_REG_TIMER_REG_READ
#define PSRAM_UHS_REG_TIMER_REG_READ_POS      (16U)
#define PSRAM_UHS_REG_TIMER_REG_READ_LEN      (8U)
#define PSRAM_UHS_REG_TIMER_REG_READ_MSK      (((1U << PSRAM_UHS_REG_TIMER_REG_READ_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_READ_POS)
#define PSRAM_UHS_REG_TIMER_REG_READ_UMSK     (~(((1U << PSRAM_UHS_REG_TIMER_REG_READ_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_READ_POS))
#define PSRAM_UHS_REG_TIMER_DQS_STOP          PSRAM_UHS_REG_TIMER_DQS_STOP
#define PSRAM_UHS_REG_TIMER_DQS_STOP_POS      (24U)
#define PSRAM_UHS_REG_TIMER_DQS_STOP_LEN      (8U)
#define PSRAM_UHS_REG_TIMER_DQS_STOP_MSK      (((1U << PSRAM_UHS_REG_TIMER_DQS_STOP_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_STOP_POS)
#define PSRAM_UHS_REG_TIMER_DQS_STOP_UMSK     (~(((1U << PSRAM_UHS_REG_TIMER_DQS_STOP_LEN) - 1) << PSRAM_UHS_REG_TIMER_DQS_STOP_POS))

/* 0x13C : phy_cfg_3C */
#define PSRAM_UHS_PHY_CFG_3C_OFFSET                 (0x13C)
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN        PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_POS    (0U)
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_LEN    (8U)
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_MSK    (((1U << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_LEN) - 1) << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_POS)
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_UMSK   (~(((1U << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_LEN) - 1) << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_IN_POS))
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT      PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_POS  (8U)
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_LEN  (8U)
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_MSK  (((1U << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_LEN) - 1) << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_POS)
#define PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_LEN) - 1) << PSRAM_UHS_REG_TIMER_SELF_REFRESH1_EXIT_POS))
#define PSRAM_UHS_REG_TIMER_GLOBAL_RST              PSRAM_UHS_REG_TIMER_GLOBAL_RST
#define PSRAM_UHS_REG_TIMER_GLOBAL_RST_POS          (16U)
#define PSRAM_UHS_REG_TIMER_GLOBAL_RST_LEN          (14U)
#define PSRAM_UHS_REG_TIMER_GLOBAL_RST_MSK          (((1U << PSRAM_UHS_REG_TIMER_GLOBAL_RST_LEN) - 1) << PSRAM_UHS_REG_TIMER_GLOBAL_RST_POS)
#define PSRAM_UHS_REG_TIMER_GLOBAL_RST_UMSK         (~(((1U << PSRAM_UHS_REG_TIMER_GLOBAL_RST_LEN) - 1) << PSRAM_UHS_REG_TIMER_GLOBAL_RST_POS))

/* 0x140 : phy_cfg_40 */
#define PSRAM_UHS_PHY_CFG_40_OFFSET       (0x140)
#define PSRAM_UHS_VREF_SEL                PSRAM_UHS_VREF_SEL
#define PSRAM_UHS_VREF_SEL_POS            (0U)
#define PSRAM_UHS_VREF_SEL_LEN            (4U)
#define PSRAM_UHS_VREF_SEL_MSK            (((1U << PSRAM_UHS_VREF_SEL_LEN) - 1) << PSRAM_UHS_VREF_SEL_POS)
#define PSRAM_UHS_VREF_SEL_UMSK           (~(((1U << PSRAM_UHS_VREF_SEL_LEN) - 1) << PSRAM_UHS_VREF_SEL_POS))
#define PSRAM_UHS_VREF_DQ_SEL             PSRAM_UHS_VREF_DQ_SEL
#define PSRAM_UHS_VREF_DQ_SEL_POS         (4U)
#define PSRAM_UHS_VREF_DQ_SEL_LEN         (4U)
#define PSRAM_UHS_VREF_DQ_SEL_MSK         (((1U << PSRAM_UHS_VREF_DQ_SEL_LEN) - 1) << PSRAM_UHS_VREF_DQ_SEL_POS)
#define PSRAM_UHS_VREF_DQ_SEL_UMSK        (~(((1U << PSRAM_UHS_VREF_DQ_SEL_LEN) - 1) << PSRAM_UHS_VREF_DQ_SEL_POS))
#define PSRAM_UHS_REG_UHS_DMY0            PSRAM_UHS_REG_UHS_DMY0
#define PSRAM_UHS_REG_UHS_DMY0_POS        (8U)
#define PSRAM_UHS_REG_UHS_DMY0_LEN        (8U)
#define PSRAM_UHS_REG_UHS_DMY0_MSK        (((1U << PSRAM_UHS_REG_UHS_DMY0_LEN) - 1) << PSRAM_UHS_REG_UHS_DMY0_POS)
#define PSRAM_UHS_REG_UHS_DMY0_UMSK       (~(((1U << PSRAM_UHS_REG_UHS_DMY0_LEN) - 1) << PSRAM_UHS_REG_UHS_DMY0_POS))
#define PSRAM_UHS_REG_UHS_DMY1            PSRAM_UHS_REG_UHS_DMY1
#define PSRAM_UHS_REG_UHS_DMY1_POS        (16U)
#define PSRAM_UHS_REG_UHS_DMY1_LEN        (8U)
#define PSRAM_UHS_REG_UHS_DMY1_MSK        (((1U << PSRAM_UHS_REG_UHS_DMY1_LEN) - 1) << PSRAM_UHS_REG_UHS_DMY1_POS)
#define PSRAM_UHS_REG_UHS_DMY1_UMSK       (~(((1U << PSRAM_UHS_REG_UHS_DMY1_LEN) - 1) << PSRAM_UHS_REG_UHS_DMY1_POS))
#define PSRAM_UHS_REG_UHS_PHY_TEN         PSRAM_UHS_REG_UHS_PHY_TEN
#define PSRAM_UHS_REG_UHS_PHY_TEN_POS     (24U)
#define PSRAM_UHS_REG_UHS_PHY_TEN_LEN     (1U)
#define PSRAM_UHS_REG_UHS_PHY_TEN_MSK     (((1U << PSRAM_UHS_REG_UHS_PHY_TEN_LEN) - 1) << PSRAM_UHS_REG_UHS_PHY_TEN_POS)
#define PSRAM_UHS_REG_UHS_PHY_TEN_UMSK    (~(((1U << PSRAM_UHS_REG_UHS_PHY_TEN_LEN) - 1) << PSRAM_UHS_REG_UHS_PHY_TEN_POS))
#define PSRAM_UHS_SOC_EN_AON              PSRAM_UHS_SOC_EN_AON
#define PSRAM_UHS_SOC_EN_AON_POS          (25U)
#define PSRAM_UHS_SOC_EN_AON_LEN          (1U)
#define PSRAM_UHS_SOC_EN_AON_MSK          (((1U << PSRAM_UHS_SOC_EN_AON_LEN) - 1) << PSRAM_UHS_SOC_EN_AON_POS)
#define PSRAM_UHS_SOC_EN_AON_UMSK         (~(((1U << PSRAM_UHS_SOC_EN_AON_LEN) - 1) << PSRAM_UHS_SOC_EN_AON_POS))
#define PSRAM_UHS_TEN_UHS_PHY             PSRAM_UHS_TEN_UHS_PHY
#define PSRAM_UHS_TEN_UHS_PHY_POS         (26U)
#define PSRAM_UHS_TEN_UHS_PHY_LEN         (1U)
#define PSRAM_UHS_TEN_UHS_PHY_MSK         (((1U << PSRAM_UHS_TEN_UHS_PHY_LEN) - 1) << PSRAM_UHS_TEN_UHS_PHY_POS)
#define PSRAM_UHS_TEN_UHS_PHY_UMSK        (~(((1U << PSRAM_UHS_TEN_UHS_PHY_LEN) - 1) << PSRAM_UHS_TEN_UHS_PHY_POS))
#define PSRAM_UHS_TEN_UHS_PHY_DIG         PSRAM_UHS_TEN_UHS_PHY_DIG
#define PSRAM_UHS_TEN_UHS_PHY_DIG_POS     (27U)
#define PSRAM_UHS_TEN_UHS_PHY_DIG_LEN     (1U)
#define PSRAM_UHS_TEN_UHS_PHY_DIG_MSK     (((1U << PSRAM_UHS_TEN_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TEN_UHS_PHY_DIG_POS)
#define PSRAM_UHS_TEN_UHS_PHY_DIG_UMSK    (~(((1U << PSRAM_UHS_TEN_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TEN_UHS_PHY_DIG_POS))
#define PSRAM_UHS_TX_CLKTREE_GATE_HW      PSRAM_UHS_TX_CLKTREE_GATE_HW
#define PSRAM_UHS_TX_CLKTREE_GATE_HW_POS  (29U)
#define PSRAM_UHS_TX_CLKTREE_GATE_HW_LEN  (1U)
#define PSRAM_UHS_TX_CLKTREE_GATE_HW_MSK  (((1U << PSRAM_UHS_TX_CLKTREE_GATE_HW_LEN) - 1) << PSRAM_UHS_TX_CLKTREE_GATE_HW_POS)
#define PSRAM_UHS_TX_CLKTREE_GATE_HW_UMSK (~(((1U << PSRAM_UHS_TX_CLKTREE_GATE_HW_LEN) - 1) << PSRAM_UHS_TX_CLKTREE_GATE_HW_POS))
#define PSRAM_UHS_UHS_DC_TP_OUT_EN        PSRAM_UHS_UHS_DC_TP_OUT_EN
#define PSRAM_UHS_UHS_DC_TP_OUT_EN_POS    (30U)
#define PSRAM_UHS_UHS_DC_TP_OUT_EN_LEN    (1U)
#define PSRAM_UHS_UHS_DC_TP_OUT_EN_MSK    (((1U << PSRAM_UHS_UHS_DC_TP_OUT_EN_LEN) - 1) << PSRAM_UHS_UHS_DC_TP_OUT_EN_POS)
#define PSRAM_UHS_UHS_DC_TP_OUT_EN_UMSK   (~(((1U << PSRAM_UHS_UHS_DC_TP_OUT_EN_LEN) - 1) << PSRAM_UHS_UHS_DC_TP_OUT_EN_POS))
#define PSRAM_UHS_UHS_PHY_DQS_DIFF        PSRAM_UHS_UHS_PHY_DQS_DIFF
#define PSRAM_UHS_UHS_PHY_DQS_DIFF_POS    (31U)
#define PSRAM_UHS_UHS_PHY_DQS_DIFF_LEN    (1U)
#define PSRAM_UHS_UHS_PHY_DQS_DIFF_MSK    (((1U << PSRAM_UHS_UHS_PHY_DQS_DIFF_LEN) - 1) << PSRAM_UHS_UHS_PHY_DQS_DIFF_POS)
#define PSRAM_UHS_UHS_PHY_DQS_DIFF_UMSK   (~(((1U << PSRAM_UHS_UHS_PHY_DQS_DIFF_LEN) - 1) << PSRAM_UHS_UHS_PHY_DQS_DIFF_POS))

/* 0x144 : phy_cfg_44 */
#define PSRAM_UHS_PHY_CFG_44_OFFSET               (0x144)
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY       PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_POS   (0U)
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_LEN   (8U)
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_MSK   (((1U << PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_POS)
#define PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_UMSK  (~(((1U << PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_READ_BUSY_POS))
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY      PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_POS  (8U)
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_LEN  (8U)
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_MSK  (((1U << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_POS)
#define PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_UMSK (~(((1U << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_ARRAY_WRITE_BUSY_POS))
#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY         PSRAM_UHS_REG_TIMER_REG_READ_BUSY
#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY_POS     (16U)
#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY_LEN     (8U)
#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY_MSK     (((1U << PSRAM_UHS_REG_TIMER_REG_READ_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_READ_BUSY_POS)
#define PSRAM_UHS_REG_TIMER_REG_READ_BUSY_UMSK    (~(((1U << PSRAM_UHS_REG_TIMER_REG_READ_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_READ_BUSY_POS))
#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY        PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY
#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_POS    (24U)
#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_LEN    (8U)
#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_MSK    (((1U << PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_POS)
#define PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_UMSK   (~(((1U << PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_LEN) - 1) << PSRAM_UHS_REG_TIMER_REG_WRITE_BUSY_POS))

/* 0x148 : phy_cfg_48 */
#define PSRAM_UHS_PHY_CFG_48_OFFSET     (0x148)
#define PSRAM_UHS_TMUX                  PSRAM_UHS_TMUX
#define PSRAM_UHS_TMUX_POS              (0U)
#define PSRAM_UHS_TMUX_LEN              (3U)
#define PSRAM_UHS_TMUX_MSK              (((1U << PSRAM_UHS_TMUX_LEN) - 1) << PSRAM_UHS_TMUX_POS)
#define PSRAM_UHS_TMUX_UMSK             (~(((1U << PSRAM_UHS_TMUX_LEN) - 1) << PSRAM_UHS_TMUX_POS))
#define PSRAM_UHS_CHIP_EN_33            PSRAM_UHS_CHIP_EN_33
#define PSRAM_UHS_CHIP_EN_33_POS        (3U)
#define PSRAM_UHS_CHIP_EN_33_LEN        (1U)
#define PSRAM_UHS_CHIP_EN_33_MSK        (((1U << PSRAM_UHS_CHIP_EN_33_LEN) - 1) << PSRAM_UHS_CHIP_EN_33_POS)
#define PSRAM_UHS_CHIP_EN_33_UMSK       (~(((1U << PSRAM_UHS_CHIP_EN_33_LEN) - 1) << PSRAM_UHS_CHIP_EN_33_POS))
#define PSRAM_UHS_TMUX_UHS_PHY_DIG      PSRAM_UHS_TMUX_UHS_PHY_DIG
#define PSRAM_UHS_TMUX_UHS_PHY_DIG_POS  (4U)
#define PSRAM_UHS_TMUX_UHS_PHY_DIG_LEN  (3U)
#define PSRAM_UHS_TMUX_UHS_PHY_DIG_MSK  (((1U << PSRAM_UHS_TMUX_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TMUX_UHS_PHY_DIG_POS)
#define PSRAM_UHS_TMUX_UHS_PHY_DIG_UMSK (~(((1U << PSRAM_UHS_TMUX_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TMUX_UHS_PHY_DIG_POS))
#define PSRAM_UHS_PSRAM_TYPE            PSRAM_UHS_PSRAM_TYPE
#define PSRAM_UHS_PSRAM_TYPE_POS        (8U)
#define PSRAM_UHS_PSRAM_TYPE_LEN        (2U)
#define PSRAM_UHS_PSRAM_TYPE_MSK        (((1U << PSRAM_UHS_PSRAM_TYPE_LEN) - 1) << PSRAM_UHS_PSRAM_TYPE_POS)
#define PSRAM_UHS_PSRAM_TYPE_UMSK       (~(((1U << PSRAM_UHS_PSRAM_TYPE_LEN) - 1) << PSRAM_UHS_PSRAM_TYPE_POS))
#define PSRAM_UHS_PU_UHS_PW1P8          PSRAM_UHS_PU_UHS_PW1P8
#define PSRAM_UHS_PU_UHS_PW1P8_POS      (11U)
#define PSRAM_UHS_PU_UHS_PW1P8_LEN      (1U)
#define PSRAM_UHS_PU_UHS_PW1P8_MSK      (((1U << PSRAM_UHS_PU_UHS_PW1P8_LEN) - 1) << PSRAM_UHS_PU_UHS_PW1P8_POS)
#define PSRAM_UHS_PU_UHS_PW1P8_UMSK     (~(((1U << PSRAM_UHS_PU_UHS_PW1P8_LEN) - 1) << PSRAM_UHS_PU_UHS_PW1P8_POS))
#define PSRAM_UHS_REG_TEST_DIV_SEL      PSRAM_UHS_REG_TEST_DIV_SEL
#define PSRAM_UHS_REG_TEST_DIV_SEL_POS  (12U)
#define PSRAM_UHS_REG_TEST_DIV_SEL_LEN  (3U)
#define PSRAM_UHS_REG_TEST_DIV_SEL_MSK  (((1U << PSRAM_UHS_REG_TEST_DIV_SEL_LEN) - 1) << PSRAM_UHS_REG_TEST_DIV_SEL_POS)
#define PSRAM_UHS_REG_TEST_DIV_SEL_UMSK (~(((1U << PSRAM_UHS_REG_TEST_DIV_SEL_LEN) - 1) << PSRAM_UHS_REG_TEST_DIV_SEL_POS))
#define PSRAM_UHS_EN_RX_FE_HW           PSRAM_UHS_EN_RX_FE_HW
#define PSRAM_UHS_EN_RX_FE_HW_POS       (15U)
#define PSRAM_UHS_EN_RX_FE_HW_LEN       (1U)
#define PSRAM_UHS_EN_RX_FE_HW_MSK       (((1U << PSRAM_UHS_EN_RX_FE_HW_LEN) - 1) << PSRAM_UHS_EN_RX_FE_HW_POS)
#define PSRAM_UHS_EN_RX_FE_HW_UMSK      (~(((1U << PSRAM_UHS_EN_RX_FE_HW_LEN) - 1) << PSRAM_UHS_EN_RX_FE_HW_POS))
#define PSRAM_UHS_REG_TEST_MUX_SEL      PSRAM_UHS_REG_TEST_MUX_SEL
#define PSRAM_UHS_REG_TEST_MUX_SEL_POS  (16U)
#define PSRAM_UHS_REG_TEST_MUX_SEL_LEN  (3U)
#define PSRAM_UHS_REG_TEST_MUX_SEL_MSK  (((1U << PSRAM_UHS_REG_TEST_MUX_SEL_LEN) - 1) << PSRAM_UHS_REG_TEST_MUX_SEL_POS)
#define PSRAM_UHS_REG_TEST_MUX_SEL_UMSK (~(((1U << PSRAM_UHS_REG_TEST_MUX_SEL_LEN) - 1) << PSRAM_UHS_REG_TEST_MUX_SEL_POS))
#define PSRAM_UHS_FORCE_FSM             PSRAM_UHS_FORCE_FSM
#define PSRAM_UHS_FORCE_FSM_POS         (19U)
#define PSRAM_UHS_FORCE_FSM_LEN         (1U)
#define PSRAM_UHS_FORCE_FSM_MSK         (((1U << PSRAM_UHS_FORCE_FSM_LEN) - 1) << PSRAM_UHS_FORCE_FSM_POS)
#define PSRAM_UHS_FORCE_FSM_UMSK        (~(((1U << PSRAM_UHS_FORCE_FSM_LEN) - 1) << PSRAM_UHS_FORCE_FSM_POS))
#define PSRAM_UHS_EN_RX_FE_DLY          PSRAM_UHS_EN_RX_FE_DLY
#define PSRAM_UHS_EN_RX_FE_DLY_POS      (20U)
#define PSRAM_UHS_EN_RX_FE_DLY_LEN      (4U)
#define PSRAM_UHS_EN_RX_FE_DLY_MSK      (((1U << PSRAM_UHS_EN_RX_FE_DLY_LEN) - 1) << PSRAM_UHS_EN_RX_FE_DLY_POS)
#define PSRAM_UHS_EN_RX_FE_DLY_UMSK     (~(((1U << PSRAM_UHS_EN_RX_FE_DLY_LEN) - 1) << PSRAM_UHS_EN_RX_FE_DLY_POS))

/* 0x14C : phy_cfg_4C */
#define PSRAM_UHS_PHY_CFG_4C_OFFSET     (0x14C)
#define PSRAM_UHS_TOUT_UHS_PHY_DIG      PSRAM_UHS_TOUT_UHS_PHY_DIG
#define PSRAM_UHS_TOUT_UHS_PHY_DIG_POS  (0U)
#define PSRAM_UHS_TOUT_UHS_PHY_DIG_LEN  (16U)
#define PSRAM_UHS_TOUT_UHS_PHY_DIG_MSK  (((1U << PSRAM_UHS_TOUT_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TOUT_UHS_PHY_DIG_POS)
#define PSRAM_UHS_TOUT_UHS_PHY_DIG_UMSK (~(((1U << PSRAM_UHS_TOUT_UHS_PHY_DIG_LEN) - 1) << PSRAM_UHS_TOUT_UHS_PHY_DIG_POS))
#define PSRAM_UHS_ODT_SEL_DLY           PSRAM_UHS_ODT_SEL_DLY
#define PSRAM_UHS_ODT_SEL_DLY_POS       (16U)
#define PSRAM_UHS_ODT_SEL_DLY_LEN       (4U)
#define PSRAM_UHS_ODT_SEL_DLY_MSK       (((1U << PSRAM_UHS_ODT_SEL_DLY_LEN) - 1) << PSRAM_UHS_ODT_SEL_DLY_POS)
#define PSRAM_UHS_ODT_SEL_DLY_UMSK      (~(((1U << PSRAM_UHS_ODT_SEL_DLY_LEN) - 1) << PSRAM_UHS_ODT_SEL_DLY_POS))
#define PSRAM_UHS_ODT_SEL_HW            PSRAM_UHS_ODT_SEL_HW
#define PSRAM_UHS_ODT_SEL_HW_POS        (20U)
#define PSRAM_UHS_ODT_SEL_HW_LEN        (1U)
#define PSRAM_UHS_ODT_SEL_HW_MSK        (((1U << PSRAM_UHS_ODT_SEL_HW_LEN) - 1) << PSRAM_UHS_ODT_SEL_HW_POS)
#define PSRAM_UHS_ODT_SEL_HW_UMSK       (~(((1U << PSRAM_UHS_ODT_SEL_HW_LEN) - 1) << PSRAM_UHS_ODT_SEL_HW_POS))

/* 0x150 : phy_cfg_50 */
#define PSRAM_UHS_PHY_CFG_50_OFFSET    (0x150)
#define PSRAM_UHS_DQ_OE_UP_P_REG       PSRAM_UHS_DQ_OE_UP_P_REG
#define PSRAM_UHS_DQ_OE_UP_P_REG_POS   (0U)
#define PSRAM_UHS_DQ_OE_UP_P_REG_LEN   (3U)
#define PSRAM_UHS_DQ_OE_UP_P_REG_MSK   (((1U << PSRAM_UHS_DQ_OE_UP_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_UP_P_REG_POS)
#define PSRAM_UHS_DQ_OE_UP_P_REG_UMSK  (~(((1U << PSRAM_UHS_DQ_OE_UP_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_UP_P_REG_POS))
#define PSRAM_UHS_DQ_OE_UP_N_REG       PSRAM_UHS_DQ_OE_UP_N_REG
#define PSRAM_UHS_DQ_OE_UP_N_REG_POS   (4U)
#define PSRAM_UHS_DQ_OE_UP_N_REG_LEN   (3U)
#define PSRAM_UHS_DQ_OE_UP_N_REG_MSK   (((1U << PSRAM_UHS_DQ_OE_UP_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_UP_N_REG_POS)
#define PSRAM_UHS_DQ_OE_UP_N_REG_UMSK  (~(((1U << PSRAM_UHS_DQ_OE_UP_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_UP_N_REG_POS))
#define PSRAM_UHS_DQ_OE_MID_P_REG      PSRAM_UHS_DQ_OE_MID_P_REG
#define PSRAM_UHS_DQ_OE_MID_P_REG_POS  (8U)
#define PSRAM_UHS_DQ_OE_MID_P_REG_LEN  (3U)
#define PSRAM_UHS_DQ_OE_MID_P_REG_MSK  (((1U << PSRAM_UHS_DQ_OE_MID_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_MID_P_REG_POS)
#define PSRAM_UHS_DQ_OE_MID_P_REG_UMSK (~(((1U << PSRAM_UHS_DQ_OE_MID_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_MID_P_REG_POS))
#define PSRAM_UHS_DQ_OE_MID_N_REG      PSRAM_UHS_DQ_OE_MID_N_REG
#define PSRAM_UHS_DQ_OE_MID_N_REG_POS  (12U)
#define PSRAM_UHS_DQ_OE_MID_N_REG_LEN  (3U)
#define PSRAM_UHS_DQ_OE_MID_N_REG_MSK  (((1U << PSRAM_UHS_DQ_OE_MID_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_MID_N_REG_POS)
#define PSRAM_UHS_DQ_OE_MID_N_REG_UMSK (~(((1U << PSRAM_UHS_DQ_OE_MID_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_MID_N_REG_POS))
#define PSRAM_UHS_DQ_OE_DN_P_REG       PSRAM_UHS_DQ_OE_DN_P_REG
#define PSRAM_UHS_DQ_OE_DN_P_REG_POS   (16U)
#define PSRAM_UHS_DQ_OE_DN_P_REG_LEN   (3U)
#define PSRAM_UHS_DQ_OE_DN_P_REG_MSK   (((1U << PSRAM_UHS_DQ_OE_DN_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_DN_P_REG_POS)
#define PSRAM_UHS_DQ_OE_DN_P_REG_UMSK  (~(((1U << PSRAM_UHS_DQ_OE_DN_P_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_DN_P_REG_POS))
#define PSRAM_UHS_DQ_OE_DN_N_REG       PSRAM_UHS_DQ_OE_DN_N_REG
#define PSRAM_UHS_DQ_OE_DN_N_REG_POS   (20U)
#define PSRAM_UHS_DQ_OE_DN_N_REG_LEN   (3U)
#define PSRAM_UHS_DQ_OE_DN_N_REG_MSK   (((1U << PSRAM_UHS_DQ_OE_DN_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_DN_N_REG_POS)
#define PSRAM_UHS_DQ_OE_DN_N_REG_UMSK  (~(((1U << PSRAM_UHS_DQ_OE_DN_N_REG_LEN) - 1) << PSRAM_UHS_DQ_OE_DN_N_REG_POS))
#define PSRAM_UHS_PHY_WL_CEN_ANA       PSRAM_UHS_PHY_WL_CEN_ANA
#define PSRAM_UHS_PHY_WL_CEN_ANA_POS   (24U)
#define PSRAM_UHS_PHY_WL_CEN_ANA_LEN   (3U)
#define PSRAM_UHS_PHY_WL_CEN_ANA_MSK   (((1U << PSRAM_UHS_PHY_WL_CEN_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_CEN_ANA_POS)
#define PSRAM_UHS_PHY_WL_CEN_ANA_UMSK  (~(((1U << PSRAM_UHS_PHY_WL_CEN_ANA_LEN) - 1) << PSRAM_UHS_PHY_WL_CEN_ANA_POS))

struct psram_uhs_reg {
    /* 0x0 : UHS_basic */
    union {
        struct {
            uint32_t reg_init_en      : 1; /* [    0],        r/w,        0x0 */
            uint32_t reg_af_en        : 1; /* [    1],        r/w,        0x0 */
            uint32_t reg_config_req   : 1; /* [    2],        r/w,        0x0 */
            uint32_t reg_config_gnt   : 1; /* [    3],          r,        0x0 */
            uint32_t reserved_4_7     : 4; /* [ 7: 4],       rsvd,        0x0 */
            uint32_t reg_mode_reg     : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_addrMB_msk   : 8; /* [23:16],        r/w,       0x1f */
            uint32_t reserved_24_27   : 4; /* [27:24],       rsvd,        0x0 */
            uint32_t reg_linear_bnd_b : 4; /* [31:28],        r/w,        0xa */
        } BF;
        uint32_t WORD;
    } UHS_basic;

    /* 0x4 : UHS_cmd */
    union {
        struct {
            uint32_t reg_glbr_pulse  : 1;  /* [    0],        w1p,        0x0 */
            uint32_t reg_srfi_pulse  : 1;  /* [    1],        w1p,        0x0 */
            uint32_t reg_srfo_pulse  : 1;  /* [    2],        w1p,        0x0 */
            uint32_t reg_regw_pulse  : 1;  /* [    3],        w1p,        0x0 */
            uint32_t reg_regr_pulse  : 1;  /* [    4],        w1p,        0x0 */
            uint32_t reserved_5_7    : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t sts_glbr_done   : 1;  /* [    8],          r,        0x0 */
            uint32_t sts_srfi_done   : 1;  /* [    9],          r,        0x0 */
            uint32_t sts_srfo_done   : 1;  /* [   10],          r,        0x0 */
            uint32_t sts_regw_done   : 1;  /* [   11],          r,        0x0 */
            uint32_t sts_regr_done   : 1;  /* [   12],          r,        0x0 */
            uint32_t sts_init_done   : 1;  /* [   13],          r,        0x0 */
            uint32_t reserved_14_23  : 10; /* [23:14],       rsvd,        0x0 */
            uint32_t sts_config_read : 8;  /* [31:24],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_cmd;

    /* 0x8 : UHS_fifo_thre */
    union {
        struct {
            uint32_t reg_mask_w_fifo_cnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reg_mask_r_fifo_rem : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_fifo_thre;

    /* 0xC : UHS_manual */
    union {
        struct {
            uint32_t reg_force_ceb_low  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_force_ceb_high : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reg_psram_resetb   : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reg_x16_mode       : 1;  /* [    3],        r/w,        0x1 */
            uint32_t reg_wrap2incr_en   : 1;  /* [    4],        r/w,        0x1 */
            uint32_t reserved_5_15      : 11; /* [15: 5],       rsvd,        0x0 */
            uint32_t reg_pck_s_div      : 3;  /* [18:16],        r/w,        0x0 */
            uint32_t reserved_19_23     : 5;  /* [23:19],       rsvd,        0x0 */
            uint32_t reg_pck_t_div      : 8;  /* [31:24],        r/w,       0x40 */
        } BF;
        uint32_t WORD;
    } UHS_manual;

    /* 0x10 : UHS_auto_fresh_1 */
    union {
        struct {
            uint32_t reg_win_cycle  : 28; /* [27: 0],        r/w,    0x27100 */
            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_auto_fresh_1;

    /* 0x14 : UHS_auto_fresh_2 */
    union {
        struct {
            uint32_t reg_refi_cycle  : 16; /* [15: 0],        r/w,       0x27 */
            uint32_t reg_win_ref_cnt : 13; /* [28:16],        r/w,     0x1000 */
            uint32_t reserved_29_31  : 3;  /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_auto_fresh_2;

    /* 0x18 : UHS_auto_fresh_3 */
    union {
        struct {
            uint32_t reg_auto_ref_thre  : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t reserved_12_15     : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t auto_refresh_level : 12; /* [27:16],          r,        0x0 */
            uint32_t reserved_28_31     : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_auto_fresh_3;

    /* 0x1C : UHS_auto_fresh_4 */
    union {
        struct {
            uint32_t reg_bust_cycle : 7;  /* [ 6: 0],        r/w,       0x1d */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_auto_fresh_4;

    /* 0x20 : UHS_psram_configure */
    union {
        struct {
            uint32_t reg_uhs_latency  : 3;  /* [ 2: 0],        r/w,        0x5 */
            uint32_t reserved_3       : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t reg_uhs_drive_st : 4;  /* [ 7: 4],        r/w,        0xa */
            uint32_t reg_uhs_bl_16    : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reg_uhs_bl_32    : 1;  /* [    9],        r/w,        0x0 */
            uint32_t reg_uhs_bl_64    : 1;  /* [   10],        r/w,        0x0 */
            uint32_t reserved_11_31   : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_psram_configure;

    /* 0x24 : UHS_psram_status */
    union {
        struct {
            uint32_t sts_uhs_latency  : 3;  /* [ 2: 0],          r,        0x5 */
            uint32_t reserved_3       : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t sts_uhs_drive_st : 4;  /* [ 7: 4],          r,        0xa */
            uint32_t sts_uhs_bl_16    : 1;  /* [    8],          r,        0x0 */
            uint32_t sts_uhs_bl_32    : 1;  /* [    9],          r,        0x0 */
            uint32_t sts_uhs_bl_64    : 1;  /* [   10],          r,        0x0 */
            uint32_t reserved_11_31   : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_psram_status;

    /* 0x28  reserved */
    uint8_t RESERVED0x28[8];

    /* 0x30 : UHS_timing_ctrl */
    union {
        struct {
            uint32_t reg_trc_cycle   : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_tcphr_cycle : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_tcphw_cycle : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_trfc_cycle  : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_timing_ctrl;

    /* 0x34 : UHS_rsvd_reg */
    union {
        struct {
            uint32_t reg_mr0_7     : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_mr2_2_0   : 3;  /* [ 3: 1],        r/w,        0x0 */
            uint32_t reg_mr2_7_6   : 2;  /* [ 5: 4],        r/w,        0x0 */
            uint32_t reserved_6_31 : 26; /* [31: 6],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_rsvd_reg;

    /* 0x38  reserved */
    uint8_t RESERVED0x38[136];

    /* 0xC0 : UHS_dbg_sel */
    union {
        struct {
            uint32_t reg_psram_dbg_en  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3      : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t reg_psram_dbg_sel : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } UHS_dbg_sel;

    /* 0xc4  reserved */
    uint8_t RESERVED0xc4[44];

    /* 0xF0 : UHS_dummy_reg */
    union {
        struct {
            uint32_t reg_psram_dummy_reg : 32; /* [31: 0],        r/w, 0xffff0000 */
        } BF;
        uint32_t WORD;
    } UHS_dummy_reg;

    /* 0xf4  reserved */
    uint8_t RESERVED0xf4[12];

    /* 0x100 : phy_cfg_00 */
    union {
        struct {
            uint32_t dqs_rdy        : 1; /* [    0],          r,        0x0 */
            uint32_t reserved_1_7   : 7; /* [ 7: 1],       rsvd,        0x0 */
            uint32_t ck_sr          : 2; /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_14 : 5; /* [14:10],       rsvd,        0x0 */
            uint32_t clk0_polarity  : 1; /* [   15],        r/w,        0x0 */
            uint32_t ck_dly_drv     : 4; /* [19:16],        r/w,        0x8 */
            uint32_t cen_sr         : 2; /* [21:20],        r/w,        0x0 */
            uint32_t reserved_22_27 : 6; /* [27:22],       rsvd,        0x0 */
            uint32_t cen_dly_drv    : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_00;

    /* 0x104 : phy_cfg_04 */
    union {
        struct {
            uint32_t reserved_0_3   : 4; /* [ 3: 0],       rsvd,        0x0 */
            uint32_t dm1_sr         : 2; /* [ 5: 4],        r/w,        0x0 */
            uint32_t reserved_6_11  : 6; /* [11: 6],       rsvd,        0x0 */
            uint32_t dm1_dly_drv    : 4; /* [15:12],        r/w,        0x8 */
            uint32_t reserved_16_19 : 4; /* [19:16],       rsvd,        0x0 */
            uint32_t dm0_sr         : 2; /* [21:20],        r/w,        0x0 */
            uint32_t reserved_22_27 : 6; /* [27:22],       rsvd,        0x0 */
            uint32_t dm0_dly_drv    : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_04;

    /* 0x108 : phy_cfg_08 */
    union {
        struct {
            uint32_t dq1_sr         : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t dq1_dly_rx     : 4; /* [11: 8],        r/w,        0x1 */
            uint32_t dq1_dly_drv    : 4; /* [15:12],        r/w,        0x8 */
            uint32_t dq0_sr         : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t dq0_dly_rx     : 4; /* [27:24],        r/w,        0x1 */
            uint32_t dq0_dly_drv    : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_08;

    /* 0x10C : phy_cfg_0C */
    union {
        struct {
            uint32_t dq3_sr         : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t dq3_dly_rx     : 4; /* [11: 8],        r/w,        0x1 */
            uint32_t dq3_dly_drv    : 4; /* [15:12],        r/w,        0x8 */
            uint32_t dq2_sr         : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t dq2_dly_rx     : 4; /* [27:24],        r/w,        0x1 */
            uint32_t dq2_dly_drv    : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_0C;

    /* 0x110 : phy_cfg_10 */
    union {
        struct {
            uint32_t dq5_sr         : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t dq5_dly_rx     : 4; /* [11: 8],        r/w,        0x1 */
            uint32_t dq5_dly_drv    : 4; /* [15:12],        r/w,        0x8 */
            uint32_t dq4_sr         : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t dq4_dly_rx     : 4; /* [27:24],        r/w,        0x1 */
            uint32_t dq4_dly_drv    : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_10;

    /* 0x114 : phy_cfg_14 */
    union {
        struct {
            uint32_t dq7_sr         : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t dq7_dly_rx     : 4; /* [11: 8],        r/w,        0x1 */
            uint32_t dq7_dly_drv    : 4; /* [15:12],        r/w,        0x8 */
            uint32_t dq6_sr         : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t dq6_dly_rx     : 4; /* [27:24],        r/w,        0x1 */
            uint32_t dq6_dly_drv    : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_14;

    /* 0x118 : phy_cfg_18 */
    union {
        struct {
            uint32_t dq9_sr         : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t dq9_dly_rx     : 4; /* [11: 8],        r/w,        0x1 */
            uint32_t dq9_dly_drv    : 4; /* [15:12],        r/w,        0x8 */
            uint32_t dq8_sr         : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t dq8_dly_rx     : 4; /* [27:24],        r/w,        0x1 */
            uint32_t dq8_dly_drv    : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_18;

    /* 0x11C : phy_cfg_1C */
    union {
        struct {
            uint32_t dq11_sr        : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t dq11_dly_rx    : 4; /* [11: 8],        r/w,        0x1 */
            uint32_t dq11_dly_drv   : 4; /* [15:12],        r/w,        0x8 */
            uint32_t dq10_sr        : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t dq10_dly_rx    : 4; /* [27:24],        r/w,        0x1 */
            uint32_t dq10_dly_drv   : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_1C;

    /* 0x120 : phy_cfg_20 */
    union {
        struct {
            uint32_t dq13_sr        : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t dq13_dly_rx    : 4; /* [11: 8],        r/w,        0x1 */
            uint32_t dq13_dly_drv   : 4; /* [15:12],        r/w,        0x8 */
            uint32_t dq12_sr        : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t dq12_dly_rx    : 4; /* [27:24],        r/w,        0x1 */
            uint32_t dq12_dly_drv   : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_20;

    /* 0x124 : phy_cfg_24 */
    union {
        struct {
            uint32_t dq15_sr        : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t dq15_dly_rx    : 4; /* [11: 8],        r/w,        0x1 */
            uint32_t dq15_dly_drv   : 4; /* [15:12],        r/w,        0x8 */
            uint32_t dq14_sr        : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t dq14_dly_rx    : 4; /* [27:24],        r/w,        0x1 */
            uint32_t dq14_dly_drv   : 4; /* [31:28],        r/w,        0x8 */
        } BF;
        uint32_t WORD;
    } phy_cfg_24;

    /* 0x128 : phy_cfg_28 */
    union {
        struct {
            uint32_t reserved_0_7     : 8; /* [ 7: 0],       rsvd,        0x0 */
            uint32_t dqs0n_dly_rx     : 4; /* [11: 8],        r/w,        0x3 */
            uint32_t dqs0_sr          : 2; /* [13:12],        r/w,        0x0 */
            uint32_t dqs0_sel         : 2; /* [15:14],        r/w,        0x0 */
            uint32_t reserved_16_19   : 4; /* [19:16],       rsvd,        0x0 */
            uint32_t dqs0_dly_rx      : 4; /* [23:20],        r/w,        0x3 */
            uint32_t dqs0_dly_drv     : 4; /* [27:24],        r/w,        0x8 */
            uint32_t dqs0_diff_dly_rx : 4; /* [31:28],        r/w,        0x3 */
        } BF;
        uint32_t WORD;
    } phy_cfg_28;

    /* 0x12C : phy_cfg_2C */
    union {
        struct {
            uint32_t ipp5un_lpddr     : 1; /* [    0],        r/w,        0x0 */
            uint32_t en_rx_fe         : 1; /* [    1],        r/w,        0x1 */
            uint32_t en_bias          : 1; /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_7     : 5; /* [ 7: 3],       rsvd,        0x0 */
            uint32_t dqs1n_dly_rx     : 4; /* [11: 8],        r/w,        0x3 */
            uint32_t dqs1_sr          : 2; /* [13:12],        r/w,        0x0 */
            uint32_t dqs1_sel         : 2; /* [15:14],        r/w,        0x0 */
            uint32_t reserved_16_19   : 4; /* [19:16],       rsvd,        0x0 */
            uint32_t dqs1_dly_rx      : 4; /* [23:20],        r/w,        0x3 */
            uint32_t dqs1_dly_drv     : 4; /* [27:24],        r/w,        0x8 */
            uint32_t dqs1_diff_dly_rx : 4; /* [31:28],        r/w,        0x3 */
        } BF;
        uint32_t WORD;
    } phy_cfg_2C;

    /* 0x130 : phy_cfg_30 */
    union {
        struct {
            uint32_t phy_wl_dq_dig : 3; /* [ 2: 0],        r/w,        0x0 */
            uint32_t reserved_3    : 1; /* [    3],       rsvd,        0x0 */
            uint32_t phy_wl_dq_ana : 3; /* [ 6: 4],        r/w,        0x2 */
            uint32_t reserved_7    : 1; /* [    7],       rsvd,        0x0 */
            uint32_t phy_wl_dig    : 3; /* [10: 8],        r/w,        0x0 */
            uint32_t reserved_11   : 1; /* [   11],       rsvd,        0x0 */
            uint32_t phy_wl_ana    : 3; /* [14:12],        r/w,        0x1 */
            uint32_t reserved_15   : 1; /* [   15],       rsvd,        0x0 */
            uint32_t phy_rl_dig    : 4; /* [19:16],        r/w,        0x3 */
            uint32_t phy_rl_ana    : 3; /* [22:20],        r/w,        0x3 */
            uint32_t reserved_23   : 1; /* [   23],       rsvd,        0x0 */
            uint32_t oe_timer      : 2; /* [25:24],        r/w,        0x2 */
            uint32_t vref_mode     : 1; /* [   26],        r/w,        0x0 */
            uint32_t oe_ctrl_hw    : 1; /* [   27],        r/w,        0x1 */
            uint32_t odt_sel       : 4; /* [31:28],        r/w,        0xa */
        } BF;
        uint32_t WORD;
    } phy_cfg_30;

    /* 0x134 : phy_cfg_34 */
    union {
        struct {
            uint32_t reg_timer_dqs_start      : 8; /* [ 7: 0],        r/w,        0x1 */
            uint32_t reg_timer_dqs_array_stop : 8; /* [15: 8],        r/w,        0x1 */
            uint32_t reg_timer_array_write    : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_timer_array_read     : 8; /* [31:24],        r/w,        0x5 */
        } BF;
        uint32_t WORD;
    } phy_cfg_34;

    /* 0x138 : phy_cfg_38 */
    union {
        struct {
            uint32_t reg_timer_auto_refresh : 8; /* [ 7: 0],        r/w,        0x7 */
            uint32_t reg_timer_reg_write    : 8; /* [15: 8],        r/w,        0x1 */
            uint32_t reg_timer_reg_read     : 8; /* [23:16],        r/w,        0x8 */
            uint32_t reg_timer_dqs_stop     : 8; /* [31:24],        r/w,        0x2 */
        } BF;
        uint32_t WORD;
    } phy_cfg_38;

    /* 0x13C : phy_cfg_3C */
    union {
        struct {
            uint32_t reg_timer_self_refresh1_in   : 8;  /* [ 7: 0],        r/w,        0x8 */
            uint32_t reg_timer_self_refresh1_exit : 8;  /* [15: 8],        r/w,        0x8 */
            uint32_t reg_timer_global_rst         : 14; /* [29:16],        r/w,      0x272 */
            uint32_t reserved_30_31               : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } phy_cfg_3C;

    /* 0x140 : phy_cfg_40 */
    union {
        struct {
            uint32_t vref_sel           : 4; /* [ 3: 0],        r/w,        0x0 */
            uint32_t vref_dq_sel        : 4; /* [ 7: 4],        r/w,        0x0 */
            uint32_t reg_uhs_dmy0       : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_uhs_dmy1       : 8; /* [23:16],        r/w,       0xff */
            uint32_t reg_uhs_phy_ten    : 1; /* [   24],        r/w,        0x0 */
            uint32_t soc_en_aon         : 1; /* [   25],        r/w,        0x1 */
            uint32_t ten_uhs_phy        : 1; /* [   26],        r/w,        0x0 */
            uint32_t ten_uhs_phy_dig    : 1; /* [   27],        r/w,        0x0 */
            uint32_t reserved_28        : 1; /* [   28],       rsvd,        0x0 */
            uint32_t tx_clktree_gate_hw : 1; /* [   29],        r/w,        0x1 */
            uint32_t uhs_dc_tp_out_en   : 1; /* [   30],        r/w,        0x0 */
            uint32_t uhs_phy_dqs_diff   : 1; /* [   31],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } phy_cfg_40;

    /* 0x144 : phy_cfg_44 */
    union {
        struct {
            uint32_t reg_timer_array_read_busy  : 8; /* [ 7: 0],        r/w,        0x8 */
            uint32_t reg_timer_array_write_busy : 8; /* [15: 8],        r/w,        0x3 */
            uint32_t reg_timer_reg_read_busy    : 8; /* [23:16],        r/w,        0xb */
            uint32_t reg_timer_reg_write_busy   : 8; /* [31:24],        r/w,        0x4 */
        } BF;
        uint32_t WORD;
    } phy_cfg_44;

    /* 0x148 : phy_cfg_48 */
    union {
        struct {
            uint32_t tmux             : 3; /* [ 2: 0],        r/w,        0x0 */
            uint32_t chip_en_33       : 1; /* [    3],        r/w,        0x1 */
            uint32_t tmux_uhs_phy_dig : 3; /* [ 6: 4],        r/w,        0x0 */
            uint32_t reserved_7       : 1; /* [    7],       rsvd,        0x0 */
            uint32_t psram_type       : 2; /* [ 9: 8],        r/w,        0x1 */
            uint32_t reserved_10      : 1; /* [   10],       rsvd,        0x0 */
            uint32_t pu_uhs_pw1p8     : 1; /* [   11],        r/w,        0x1 */
            uint32_t reg_test_div_sel : 3; /* [14:12],        r/w,        0x0 */
            uint32_t en_rx_fe_hw      : 1; /* [   15],        r/w,        0x1 */
            uint32_t reg_test_mux_sel : 3; /* [18:16],        r/w,        0x0 */
            uint32_t force_fsm        : 1; /* [   19],        r/w,        0x0 */
            uint32_t en_rx_fe_dly     : 4; /* [23:20],        r/w,        0x2 */
            uint32_t reserved_24_31   : 8; /* [31:24],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } phy_cfg_48;

    /* 0x14C : phy_cfg_4C */
    union {
        struct {
            uint32_t tout_uhs_phy_dig : 16; /* [15: 0],          r,        0x0 */
            uint32_t odt_sel_dly      : 4;  /* [19:16],        r/w,        0x3 */
            uint32_t odt_sel_hw       : 1;  /* [   20],        r/w,        0x1 */
            uint32_t reserved_21_31   : 11; /* [31:21],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } phy_cfg_4C;

    /* 0x150 : phy_cfg_50 */
    union {
        struct {
            uint32_t dq_oe_up_p_reg  : 3; /* [ 2: 0],        r/w,        0x4 */
            uint32_t reserved_3      : 1; /* [    3],       rsvd,        0x0 */
            uint32_t dq_oe_up_n_reg  : 3; /* [ 6: 4],        r/w,        0x4 */
            uint32_t reserved_7      : 1; /* [    7],       rsvd,        0x0 */
            uint32_t dq_oe_mid_p_reg : 3; /* [10: 8],        r/w,        0x4 */
            uint32_t reserved_11     : 1; /* [   11],       rsvd,        0x0 */
            uint32_t dq_oe_mid_n_reg : 3; /* [14:12],        r/w,        0x4 */
            uint32_t reserved_15     : 1; /* [   15],       rsvd,        0x0 */
            uint32_t dq_oe_dn_p_reg  : 3; /* [18:16],        r/w,        0x4 */
            uint32_t reserved_19     : 1; /* [   19],       rsvd,        0x0 */
            uint32_t dq_oe_dn_n_reg  : 3; /* [22:20],        r/w,        0x4 */
            uint32_t reserved_23     : 1; /* [   23],       rsvd,        0x0 */
            uint32_t phy_wl_cen_ana  : 3; /* [26:24],        r/w,        0x1 */
            uint32_t reserved_27_31  : 5; /* [31:27],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } phy_cfg_50;
};

typedef volatile struct psram_uhs_reg psram_uhs_reg_t;

#endif /* __PSRAM_UHS_REG_H__ */
